Patents by Inventor Grady L. Giles

Grady L. Giles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100464
    Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: September 24, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Joel Thornton Irby, Grady L. Giles
  • Patent number: 11657892
    Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 23, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Joel Thornton Irby, Grady L. Giles
  • Patent number: 9046574
    Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 2, 2015
    Assignee: ADVANCED MICRO DEVICES, INC
    Inventors: Grady L. Giles, James A. Wingfield, Atchyuth K. Gorti
  • Publication number: 20140149813
    Abstract: A test circuit for a functional circuit includes a scan chain coupled to the functional circuit, and a controller coupled to the scan chain, for controlling the scan chain to scan a test pattern into the scan chain, and subsequently and repetitively for a multiple number of times launch the test pattern to the functional circuit, capture test data into the scan chain, and restore the test pattern in the scan chain for subsequent launch.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Grady L. Giles, James A. Wingfield, Atchyuth K. Gorti
  • Patent number: 8103924
    Abstract: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: January 24, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Grady L. Giles, Brian Hoang, Timothy J. Wood
  • Patent number: 7925937
    Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 12, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joel T. Irby, Grady L. Giles, Alexander W. Schaefer, Gregory A. Constant, Floyd L. Dankert, Amy M. Novak
  • Publication number: 20090193303
    Abstract: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Inventors: Grady L. Giles, Brian Hoang, Timothy J. Wood
  • Publication number: 20090177934
    Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Inventors: Joel T. Irby, Grady L. Giles, Alexander W. Schaefer, Gregory A. Constant, Floyd D. Dankert, Amy M. Novak
  • Patent number: 5889788
    Abstract: An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the embedded core are available at external terminals of the integrated circuit (10). Therefore, the wrapper speed path test cells (16 and 18) are provided. The cell (16) contains two flip-flops (20 and 22) which can be used to launch logic transitions into the embedded core (14) to perform two clock speed path testing. The cell (18) contains flip-flops (26 and 28) which can perform a speed path launch operations to a customer specified logic (12). The cell (16) can perform speed path capture operations for the customer specified logic (12) whereas the cell (18) can perform speed path capture operations for the embedded core (14).
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: March 30, 1999
    Assignee: Motorola, Inc.
    Inventors: Matthew D. Pressly, Grady L. Giles, Alfred L. Crouch
  • Patent number: 5812561
    Abstract: A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: September 22, 1998
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Alfred Larry Crouch, Odis Dale Amason, Jr., Matthew Donald Pressly, Clark Gilson Shepard, Michael Alan Mateja, Lee Allen Corley, Daniel T. Marquette, Jason E. Doege
  • Patent number: 5774476
    Abstract: Wrapper cells (16 and 18) are coupled to inputs and outputs of an embedded core (14) within an integrated circuit (10). The wrapper cells (16 and 18) are used to test timing specifications of the embedded core after the embedded core has been integrated on-chip with other peripheral logic (12). In order to accurately measure the timing specifications, test circuits (FIGS. 6-8) are formed on chip with the wrapper where the test circuits are used to measure clock skew a like internal integrated circuit (IC) parameters. The clock skew and other measured internal IC parameters are used to accurately test the timing specification of the embedded core with reduced uncertainty.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 30, 1998
    Assignee: Motorola, Inc.
    Inventors: Matthew D. Pressly, Grady L. Giles
  • Patent number: 5369752
    Abstract: A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: November 29, 1994
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, William D. Atwell, Jr., Jesse R. Wilson, Richard B. Reis
  • Patent number: 5220526
    Abstract: An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is identical to information previously stored in the system. However, the Match line signal associated with the predetermined row is disabled by a predetermined transistor (14, 16, 18, 20) when the row is written. Because information is simultaneously presented in parallel to other rows in the CAM system, a Match line signal is asserted if the information currently written to the predetermined row is identical to information previously written to another row in the CAM system. Any asserted Match line signal which was not disabled indicates to the user of the CAM system that two or more entries are identical in the CAM array.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: June 15, 1993
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Yui K. Ho, Robert B. Cohen
  • Patent number: 5015875
    Abstract: A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: May 14, 1991
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Jesse R. Wilson
  • Patent number: 4680760
    Abstract: Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: July 14, 1987
    Assignee: Motorola, Inc.
    Inventors: Grady L. Giles, Jesse R. Wilson, Terry V. Hulett