Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

Abstract: A current averaging circuit for averaging a piecewise linear switching current waveform of a PWM power converter including first, second and third sample and hold circuits and a sample averaging circuit. The first sample and hold circuit samples a short duration of the current waveform for each PWM cycle and provides corresponding short samples. The second sample and hold circuit samples a long duration of each PWM cycle and provides corresponding long samples. The sample averaging circuit is coupled to the first and second sample and hold circuits, averages corresponding ones of the short and long samples and provides corresponding average values. The third sample and hold circuit samples each average value and provides a current average signal. The waveform may include ramp-on-a-step voltage pulses representing switching current. The current average signal is updated after each current pulse.

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.

Abstract: A multiplexed high voltage DC-AC driver including multiple DC-AC switches and decoder logic. Each DC-AC switch receives an input DC voltage and is operative, when enable, to toggle its output at a rate based on a master clock signal and at a voltage based on the input DC voltage. The DC-AC switches include one or more high side switches and a low side switch. The low side switch includes a clock inverter and operates out-of-phase relative to each high side switch. The decoder logic enables selected ones of the high side switches and enables the low side switch when any high side switch is enabled.

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.

Abstract: A switch includes first and second switch terminals, at least one output MOS transistor for selectively connecting the first and second switch terminals, and a driving current source for driving the at least one output MOS transistor. The switch may also include a current limiter for limiting the driving of the at least one output MOS transistor by the driving current source to establish a current limit. Furthermore, a controller may be included for the current limiter for controlling the current limit, such as by causing the current limiter to decrease the current limit based upon an increase in temperature of the integrated circuit or at periodic intervals to control rise and fall times of the at least one output MOS transistor.

Abstract: A switch includes first and second switch terminals, at least one output MOS transistor for selectively connecting the first and second switch terminals, and a driving current source for driving the at least one output MOS transistor. The switch may also include a current limiter for limiting the driving of the at least one output MOS transistor by the driving current source to establish a current limit. Furthermore, a controller may be included for the current limiter for controlling the current limit, such as by causing the current limiter to decrease the current limit based upon an increase in temperature of the integrated circuit or at periodic intervals to control rise and fall times of the at least one output MOS transistor.

Abstract: A driver for an EL lamp includes a voltage detector coupled to the lamp for monitoring the voltage across the lamp and providing an indication of when the lamp is substantially discharged.

Abstract: In a switching inverter where switches are controlled so as to provide current through an inductor which is connected in series with other switches across a battery so as to power a capacitive load, such as an electroluminescent lamp, with higher voltage than the battery voltage, the other switches, which may be SCRs, provide a path for current which charges and discharges the lamp to provide the higher voltage as an alternating voltage across the load. These other switches are switched on in synchronism with pulses of current which are produced in the inductor by circuits providing capacitances at the triggering terminals of the other switches (control electrodes or gates in the case of SCRs). These circuits are connected to the inductor so that transients or spikes, occurring when the current through the conductor is switched, enable triggering current flow with respect to the capacitances. This triggering current flow automatically triggers the other switching devices.

Abstract: An electroluminescent lamp driver system for driving or powering an electroluminescent lamp to illuminate the display in an electronic watch, such as a quartz analog watch, uses the counter in a CMOS timekeeping chip which counts down the quartz oscillator frequency to one Hz for an analog quartz watch. The counter provides a plurality of pulse trains which are combined in digital logic to provide switching signals. The digital logic is included in the timekeeping chip and is implemented in low voltage bulk CMOS. A high voltage is required to drive the lamp and it is provided in a separate chip containing a high voltage inverter in which current is switch through an inductor in response to the switching signals from the timekeeping chip.

Abstract: In a switching inverter where transistor switches are controlled so as to provide current through an inductor which is connected in series with the switches across a battery so as to power a capacitive load (such as an electroluminescent lamp) with higher voltage than the battery voltage, control current for the switches and particularly the emitter to base current therethrough is shared by connecting the bases of these transistors via a current limiting resistor. Using the same base current reduces the battery drain and improves the efficiency (power applied to the load versus battery power drawn) of the inverter.

Abstract: A band-gap reference having a differential amplifier with first and second inputs and an output, and a voltage divider coupled to the differential amplifier output. A first transistor having a base, emitter and collector, has its base coupled to the voltage divider, the first transistor having an emitter current density of x. A second transistor having a base, emitter and collector, has its base coupled to the voltage divider, the second transistor having an emitter current density of nx, where n is fixed. A third transistor having a base, emitter and collector, has its base coupled to the emitter of the first transistor, and its collector coupled to the first input of the differential amplifier. A fourth transistor having a base, emitter and collector, has its base coupled to the emitter of the second transistor, and its collector coupled to the second input of the differential amplifier, and the emitter of the fourth transistor being coupled to the emitter of the third transistor.

Abstract: A single input/multiple output NOR gate employs a reference voltage source for establishing the operational level of a multiple output current logic driver transistor. As the reference voltage source, the forward base-emitter voltage V.sub.be of a second transistor is used. Coupled between the current logic driver transistor and the second transistor is a multiple emitter diode-connected input transistor. One of the emitters of the input transistor is coupled in the current flow path from the current logic driver transistor to a current control resistor that is coupled in parallel with the base-emitter junction of the reference transistor, while a second emitter of the input transistor is coupled to the collector-emitter current flow path of the second (reference) transistor.In the absence of the application of current to the input transistor, the voltage level at the input is effectively equal to the sum of the forward base-emitter voltage drops of the input and second transistors.

Abstract: A TTL gate for driving large capacitive loads with minimal current drain of the gate's power supply during the logic low output level is provided. The current drain from the power supply is minimized by a feedback means which becomes active when the logic low output level is reached. The feedback means comprises a current mirror circuit connected between the drive means and the output means of the gate. The drive means also comprises a current mirror circuit.

Abstract: The first fire voltage of amorphous memory devices are reduced by forming the storage element of two layers, the first being in the crystalline state and the second being the amorphous state. The process deposits a first layer of switchable material and raises the temperature to crystallize the first layer. The wafer is then cooled and the remainder of the switchable material to form the storage element is deposited in an amorphous state.

Abstract: A current source having two current paths connected as current mirrors with an amorphous material device in one of the current paths which is electrically alterable from a high impedance state to lower high impedance states without switching to a low impedance state. A diode interconnects the amorphous material element to the current path to prevent damage to the current path during electrical alteration of the amorphous material device. The current source is included in a differential amplifier and operational amplifier to provide fine incremental trim or offset adjustment.

Abstract: The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.

Abstract: The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.