Abstract: A method to look at the incoming received data on a SerDes link while running in normal operation without requiring a second receive path or any defined or repeated data patterns to be able to generate statistical eye plots both before and after any internal equalization; generate trajectory eye plots both before and after any internal equalization; estimate TED characteristics (hence also estimate SJ jitter tolerance of the link); estimate complete Channel Impulse Response (hence also estimate the S-parameters of the complete channel); and estimate the decomposed jitter of the complete channel.

Abstract: The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater.

Abstract: Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.

Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Abstract: A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.

Abstract: A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.

Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Abstract: Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Abstract: An apparatus and method for restoring digital pulses within a data transmission system which have degraded due to the attenuation and distortion inherent in a data transmission medium. The apparatus comprises an adaptive equalizer which receives signals from the data transmission medium, while the method by which the digital pulses are restored comprises: storing plural equalizer transfer function control values in a memory, passing the signal through an equalizer having a controllable transfer function, comparing a characteristic of the output signal of the equalizer with a reference signal and producing a difference signal, using the difference signal to select a set of stored transfer function control values from the memory, controlling the equalizer from the selected transfer function control values so as to minimize their difference from the reference signal. This apparatus and method are suitable for high-speed applications such as T1 and E1, requiring minimal configuration by the user.

Abstract: An integrated circuit fuse with a fuse element having an "open" state and a "closed" state. A fuse status indicator is provided to indicate whether the fuse element is "open" or "closed". A current driver is electrically connected between the fuse element and electrical ground. One input of a dual input multiplexer is electrically connected to the fuse status indicator. The multiplexer's other input receives a fuse status simulation signal. A simulation mode switching signal is applied to the multiplexer's select input. A fuse output signal is consequently provided at the multiplexer's output to simulate operation of the fuse element in either the "open" or the "closed" state. The fuse element can be opened by causing a current having a value exceeding a preselected minimum value to flow through the fuse element for a preselected minimum time.

Abstract: A circuit for training a trainable filter circuit having an adjustable time constant, the circuit having a clock generator operative to generate first and second clock signals on first and second clock signal outputs, respectively, of substantially the same amplitude and frequency. A first circuit has a reference filter circuit coupled to the first clock signal output and the second clock signal has the trainable filter circuit coupled to the second clock signal output. Means for adjusting one of the voltage input to and time constant of the reference circuit are provided. An amplifier coupled to an output of the reference circuit and to an output of the trainable filter circuit is operative to produce a DC output when the amplitudes of signals on the reference circuit output and the training circuit output are equal and an AC signal when they are unequal.

Abstract: An impedance generator, especially suitable for determining a terminating impedance of an active impedance telephone line interface circuit, comprises a subtracting circuit for forming a difference between an input voltage multiplied by a multiplier and a high pass filtered version of the difference multiplied by another multiplier, and a summing circuit for combining the input voltage multiplied by a further multiplier with a low pass filtered version of said difference to produce an output voltage. In one arrangement, the input voltage multiplied by the further multiplier constitutes a third input to the subtracting circuit. The high pass filtered version of the difference is produced by subtracting the output of a low pass filter from the difference. The multipliers are constituted by controllable gain elements, enabling the generated impedance to be easily programmed under digital control.