Abstract: A storage device system receives read commands from a host device and maintains a read disturb count for distinct zones of each of a plurality of non-volatile memory blocks in the storage device. The read disturb count for each zone corresponds to read operations performed in the zone and in predefined memory portions neighboring the zone. In accordance with a determination that the read disturb count for any zone satisfies predefined threshold criteria, the storage device performs a validation operation on one or more memory portions corresponding to that zone. If the validation operation is unsuccessful, the storage device resets the read disturb count for the zone and initiates a refresh operation on at least a portion of the corresponding block. If the validation operation is successful, the storage device resets the read disturb count for the zone that satisfied the predefined threshold criteria, and forgoes initiating the refresh operation.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A hard disk simulator that comprises a timing generator controller coupled to receive address, data and control signals; a timing generator for providing a pulse in response to signals received from the timing generator controller; and an address generator coupled to receive the control or index pulse and a programmable frequency clock to generate addresses for a hard disk simulator. The address generator includes an offset counter that generates values in response to the programmable frequency clock and the control pulse. The address generator also receives a base address that corresponds to a hard disk track. The offset counter values and the base address are combined to provide an address. The present invention also includes a method of simulating a hard disk including the step of adding an offset value to a base value to simulate rotational latency of the hard disk.

Abstract: The present invention is a method to minimize the firmware overhead for multi-track transfers. To this end, the present invention provides a transfer control table. The table is used to manage sector defects or other transfer adjustments. Each entry of the table contains an affected PSA and a corresponding control instruction. The control instruction includes an action such as an interrupt/branch, take no action, skip the sector or skip the following indicated sectors. The interrupt/branch bit causes an preferably when the last sector of a track has been read or written. The table is either entirely generated at the same time or is generated to provide for a track transfer. In the latter case, the remaining table entries are generated during the platter revolution or the track seek. The method provides for minimum microprocessor intervention. To that end, the microprocessor is interrupted only at the end of the multi-track transfer.

Abstract: In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of initiator IDs in cache entries. Based on the initiator ID in a selection command, the target selects the appropriate parameters and automatically transitions to data transfer mode. Low cost support for all initiators is thus provided.

Abstract: A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts.

Abstract: A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address.

Abstract: In a SCSI controller, unexpected messages are automatically received in response to an attention signal by receiving all of the bytes constituting the message and storing those bytes in an available register file selected from a plurality of register files in the controller. Once the entire message has been received and stored, a determination of an appropriate response is initiated. The register files are also used to hold selection information during a bus-initiated selection, so additional architecture is not required.