Abstract: A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications.

Abstract: A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications.

Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.

Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.

Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.

Abstract: A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non real-time) the available resources and sharing a plurality of processing elements with a plurality of controller elements achieve this. In a preferred embodiment the integrated circuit includes a plurality of processing blocks, which interface to a reconfigurable interconnection means. A processing block has two forms, namely a shared resource block and a dedicated resource block. Each processing block consists of one or a plurality of controller elements and a plurality of processing elements. The controller element and processing element generally comprise diverse rigid coarse and fine grained circuits and are interconnected through dedicated and reconfigurable interconnect. The processing blocks can be configured as a hierarchy of blocks and or fractal architecture.

Abstract: A data unit receives data packets and delivers them to packet switching circuitry. The data unit stores the received data packets in a memory. The memory has receive queues (RQ0 to RQ63) corresponding respectively to the different possible intended destinations of the receive packets in the packet switching circuitry, and when each data packet is received, an entry corresponding to the packet concerned is made in that one of the receive queues (RQ) which corresponds to the intended destination of the packets. A multicast handling section operates, when such a received data packet is a multicast packet having two or more intended destinations, to cause the packet registration means to make an entry corresponding to the multicast packet concerned in each receive queue corresponding to one of those destinations.

Abstract: A switching apparatus, for use in an ATM network, includes a switch fabric for switching ATM cells, a segmentation-and-reassembly device for reassembling packets from ATM cells, and a plurality of traffic management devices. Each traffic management device receives ATM cells delivered to associated ports of the apparatus and is connected by a first data delivery path to the switch fabric and by a second data delivery path directly to the segmentation-and-reassembly device. The traffic management device identifies those received ATM cells that belong to one or more predetermined types of packets, requiring reassembly by the segmentation-and-reassembly device, as respective reassembly cells. The traffic management device then delivers received cells other than such identified reassembly cells to the switch fabric via its first data delivery path for switching by the switch fabric, and then delivers the reassembly cells to the SAR device via the second data delivery path for reassembly into packets.

Abstract: Switching apparatus, for use in an ATM network for example, which includes a plurality of data units; cross-connect switching units, having a plurality of input ports and output ports, for providing data transfer paths, each path serving to pass data received at one of the input ports to one of the output port; and connection units connected to the input ports and to the data units, for delivering data from designated source data units to respective input ports and for delivering the data, after passage through one of the data transfer paths, from the output ports to respective designated destination data units. Two data units, which together constitute a data delivery group associated with an input port, are connected to each connection unit and the connection unit serves to deliver data from the two different data units of the data delivery group, at different respective times, to that associated input port. In such apparatus the number of input ports of the switching units is reduced.

Abstract: A switching apparatus provides adaptive high-speed operation in an asynchronous transport mode (ATM) network. The switching apparatus includes a number of switch units, with each switch unit further including storage regions corresponding to other switch units. The switching apparatus has a writing phase in which a first switch unit stores received data in its storage region that corresponds to a second switch unit. During the writing phase, data is received by the first switch unit for later output by a second switch unit. Then, in a reading phase, the second switch unit retrieves the stored data from its corresponding storage region in the first switch unit and then outputs the retrieved data. In both phases, the switch units operate simultaneously under control of a control unit which monitors traffic flow conditions and selects data transfer paths within the switch to achieve optimum data throughput.