Abstract: A digital-to-analog converter comprises a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit comprising switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during a precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

Abstract: A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gates of the transistors T1 and T2 receive a shifted version of the direct input signal IN from a source-follower comprising the transistors T3 and T4.

Abstract: An active matrix display comprises an active matrix 1 and a digital data driver 30 formed on a common substrate 100 by a common integration process. The driver 30 comprises a serial to parallel converter 20 having m registers forming at least one set for storing display data for m picture elements, where m is less than the number M of data lines of the matrix 1. The outputs of the registers are connected to m digital/analogue converters 21 whose outputs are connected to m bus lines 50 of an m phase analogue driver 22 in the form of a switching network. The switching network connects in turn groups of m physically adjacent data lines of the matrix 1 to the m bus line, respectively.

Abstract: Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

Abstract: A driving arrangement for an active matrix liquid crystal display comprises: (a) a multi-format digital data driver arranged to operate in a plurality of different display modes, to receive digital input data in a plurality of different formats, and to drive data lines of the liquid crystal display so as to cause an image to be displayed in the display corresponding to said input data; and (b) data analysis means arranged to receive said digital input data, to determine the format of the input data, and to control the data driver to operate in the display mode corresponding to the format of the input data. There is provided a method of reducing power required to display a sequence of images on a liquid crystal display, in which images are analysed and if consecutive Images are substantially the same, then the liquid crystal display is not updated with the subsequent image.

Abstract: A static clock pulse generator comprises a plurality of stages 1,2, each of which comprises a D-type flip-flop 3 and a gating circuit 4. The flip-flop 3 supplies output signals Q of the stage which are also used as gating signals for the gating circuit 4 of the following stage. The gating circuit 4 supplies a signal to the data input D of the flip-flop 3 when its gating input G is active and a clock pulse is present on the clock input CK or !CK. An asynchronous reset signal R is supplied to the flip-flop 3 from the following stage.

Abstract: The present invention relates to a digital-to-analog converter for converting a parallel digital input signal to a corresponding analogue output voltage, the digital-to-analogue comprising: an input arranged to receive said digital input signal; an output for outputting said corresponding analogue output voltage; and conversion means, operatively coupled to said input and said output, for moving said output voltage from a reference value to a first value and then subsequently back to said reference value, wherein the magnitude of said first value corresponds with the value of the said digital input signal, said output voltage is moved from said reference value to said first value in at least two steps via one or more intermediate values, and said output voltage is moved from said first value back to said reference value in at least two steps via one or more intermediate values.

Abstract: A data line driver is provided for driving M data lines of a matrix display such as a liquid crystal display. The driver comprises x data line circuits whose inputs are connected to a common input for receiving a serial image signal, where x is less than M. Each of the data line circuits comprises a store for storing one picture element of image data at a time, a multiplexer for storing in the store in sequence image data for m picture elements from at least part of a line of image data, where m is greater than one, and a demultiplexer for directing a line signal corresponding to the image data stored in the store to each of m of the M data lines in sequence.

Abstract: An active matrix drive circuit includes a clock element arranged so as to generate a clock signal CK; a shift register including a chain of control shift elements having respective outputs; and a series of driver stages coupled to said outputs and controllable by control signals for sampling an input signal and for supplying the sampled signals to a corresponding series of lines. Each of the driver stages is associated with a respective one of the control shift elements and is locally controlled by a plurality of different control signals derived from signals generated by said one control shift element and/or at least one local control shift element in the vicinity of said one control shift element in the shift register in response to clocking of the shift register by the clock signal CK.

Abstract: A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.

Abstract: A voltage level converter for converting an input signal at a first voltage level to an output signal at a second voltage level, the converter comprises: an input for receiving said input signal; an output for outputting said output signal; a circuit node; precharge means for charging or discharging said circuit node to a third voltage level during a first time period by connection of said circuit node to a first voltage supply; isolation means for isolating said circuit node from said first voltage supply during a second time period; input means for changing the voltage at said circuit node in dependence on the voltage at said input during a third time period; and output means arranged so that the voltage at said output depends on the voltage at said circuit node.

Abstract: A data line driver circuit for an active matrix liquid crystal display comprises a distributed controller in the form of a control shift register comprising a chain of control DFF's and associated detection logic. Furthermore the drive circuit includes a respective driver stage under the control of each control DFF for sampling the n-bit digital input signal and for supplying a drive signal to a corresponding data line. Each of the driver stages incorporates an n-bit vertically connected sample shift register composed of DFF's and associated 2:1 multiplexers which are used to provide an input either from the relevant bit line of the n-bit input data bus or from the output of the preceding DFF. In operation the n-bits of the input signal are supplied in parallel to the n inputs of the DFF's in a sampling mode, and the n-bits are shifted along the sample shift register towards the output of the shift register in a shifting mode.

Abstract: A non-linear digital-to-analog converter includes: a k bit parallel input; a decoding circuit having M inputs connected to M most significant bits of the parallel input, the decoding circuit being arranged to connect first and second consecutive reference inputs among 2.sup.m +1 reference inputs to first and second outputs, respectively, where M>m; and a variable resolution linear digital-to-analog converter having first and second reference inputs connected to the first and second outputs of the decoding circuit, respectively, and further having N digital inputs connected to N least significant bits of the parallel input, where (M+N)>k.

Abstract: A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.

Abstract: A fault tolerant circuit arrangement comprises a plurality of replicated non-redundant shift registers 30 connected in parallel and each having an enable/configuration input 31 and a plurality of outputs 36. Furthermore each register 30 includes a verify output 32 for outputting a verify signal indicating whether or not a fault condition is present within the register. The arrangement also includes a verification signal generator 33 for applying a fixed reference signal, a comparator 34 to which the verify signals from the outputs 32 are applied, and a control circuit 35. The test/control-logic of the comparator 34 and control circuit 35 is constructed using masking redundancy 20-24 in order to render the test/control logic tolerant to faults. The control circuit 35 serves to control testing of each of the registers 30 in turn by supplying an enable signal to the input 31 of each register 30 beginning with the first register. This causes the supply of a verify signal V.sub.