Patents by Inventor Graham Balsdon
Graham Balsdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853671Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 8, 2021Date of Patent: December 26, 2023Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 11030374Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 23, 2020Date of Patent: June 8, 2021Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 10691858Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: September 19, 2017Date of Patent: June 23, 2020Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 9767242Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 4, 2013Date of Patent: September 19, 2017Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 8966425Abstract: A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.Type: GrantFiled: March 14, 2013Date of Patent: February 24, 2015Assignee: Pulsic LimitedInventors: Robert Eisenstadt, Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8949760Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: GrantFiled: January 9, 2012Date of Patent: February 3, 2015Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Patent number: 8751996Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: December 11, 2012Date of Patent: June 10, 2014Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Patent number: 8479141Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: January 17, 2012Date of Patent: July 2, 2013Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8458636Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: March 18, 2010Date of Patent: June 4, 2013Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 8332805Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: July 11, 2011Date of Patent: December 11, 2012Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Publication number: 20120110539Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: PULSIC LIMITEDInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Patent number: 8171447Abstract: A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.Type: GrantFiled: March 20, 2009Date of Patent: May 1, 2012Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 8099700Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: January 17, 2012Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8095903Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: GrantFiled: October 31, 2006Date of Patent: January 10, 2012Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Patent number: 8010928Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: March 14, 2008Date of Patent: August 30, 2011Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Patent number: 7823113Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: September 11, 2006Date of Patent: October 26, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 7802208Abstract: A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.Type: GrantFiled: August 14, 2007Date of Patent: September 21, 2010Assignee: Pulsic LimitedInventors: Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 7784010Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: June 1, 2004Date of Patent: August 24, 2010Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 7530040Abstract: A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.Type: GrantFiled: May 16, 2006Date of Patent: May 5, 2009Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 7373628Abstract: A technique will automatically route interconnect of an integrated circuit. In an implementation, the technique operates on a gridless layout. The technique forms a Steiner tree for a net and routs using the Steiner tree. In a specific embodiment, the technique creates tracks having varying widths.Type: GrantFiled: May 16, 2006Date of Patent: May 13, 2008Assignee: Pulsic LimitedInventors: Graham Balsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato