Abstract: Table lookup from hardware data storage is managed as part of processing one or more computer programs operating on a data processing system. At least one request is received from the one or more computer programs for a table lookup, at a software component that is operating on the data processing system separately or segregated from the one or more computer programs. The software component retrieves the table lookup data corresponding with the at least one request from the hardware data storage. The retrieved table lookup data is returned to the one or more computer programs.

Abstract: A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.

Abstract: Table lookup from hardware data storage is managed as part of processing one or more computer programs operating on a data processing system. At least one request is received from the one or more computer programs for a table lookup, at a software component that is operating on the data processing system separately or segregated from the one or more computer programs. The software component retrieves the table lookup data corresponding with the at least one request from the hardware data storage. The retrieved table lookup data is returned to the one or more computer programs.

Abstract: A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.

Abstract: A size M×N sparse matrix, including zero values, is multiplied with a size N vector, using a processor arrangement. A data storage linked to the processor arrangement stores the matrix in a compressed formal. Zero values are not stored. The data storage stores the vector as vector parts, each of a respective size Ki, 1<Ki<N and i=1 . . . P. A vector part comprises a vector element in common with another vector part. Each vector part is stored in a distinct memory block. Each of a plurality of the non-zero values of a matrix row is associated with a memory block storing an element of the vector having an index corresponding with a respective index of the non-zero value. The processor arrangement multiplies, in parallel, each of the plurality of the non-zero values of the matrix row by the respective vector element having a corresponding index stored in the associated memory block.

Abstract: A size M×N sparse matrix, including zero values, is multiplied with a size N vector, using a processor arrangement. A data storage linked to the processor arrangement stores the matrix in a compressed formal. Zero values are not stored. The data storage stores the vector as vector parts, each of a respective size Ki, 1<Ki<N and i=1 . . . P. A vector part comprises a vector element in common with another vector part. Each vector part is stored in a distinct memory block. Each of a plurality of the non-zero values of a matrix row is associated with a memory block storing an element of the vector having an index corresponding with a respective index of the non-zero value. The processor arrangement multiplies, in parallel, each of the plurality of the non-zero values of the matrix row by the respective vector element having a corresponding index stored in the associated memory block.

Abstract: To simulate the effect of shadows in an image being rendered a light source bounding frustum is produced for a tile for a light source, and used to determine a set of geometry for the tile that could cast a shadow in the tile. The determined set of geometry is then used to determine a light source visibility parameter for each sampling position in the tile by determining for each tile screen space sampling position, whether rays cast between the tile sampling position and a set of sampling positions representing the light source would intersect occluding geometry or not. The determined number of visible light source sampling positions for each tile sampling position is used to determine a light source visibility parameter value for each tile sampling position, and the determined light source visibility parameters are then used to modulate the light source when shading the geometry.

Abstract: To simulate the effect of shadows in an image being rendered a light source bounding frustum is produced for a tile for a light source, and used to determine a set of geometry for the tile that could cast a shadow in the tile. The determined set of geometry is then used to determine a light source visibility parameter for each sampling position in the tile by determining for each tile screen space sampling position, whether rays cast between the tile sampling position and a set of sampling positions representing the light source would intersect occluding geometry or not. The determined number of visible light source sampling positions for each tile sampling position is used to determine a light source visibility parameter value for each tile sampling position, and the determined light source visibility parameters are then used to modulate the light source when shading the geometry.