Abstract: A receiver circuit for data in NRZ1 coding transmitted at high data rates along optical fiber links, wherein in order to overcome problems of phase jitter in the incoming signal, a clock circuit is included comprising a phase locked loop with voltage controlled oscillator for generating a clock signal locked in phase to the incoming data signal, a phase detector for comparing the clock signal with the incoming data signal, a phase frequency detector for comparing the clock signal with a reference clock signal, a multiplexer for switching the phase locked loop to respond either to the output of the phase detector or the phase freqency detector, and a digital counting system for comparing the number of clock pulses generated in a reference period determined by the reference clock, the digital counting system controlling the multiplexer to switch to the output of the phase detector when it is determined that the clock signal is accurately following the reference clock signal.

Abstract: A circuit for recovering clock information from an incoming data signal preferably in NRZ1 form, the circuit including a VCO (18) providing a clock signal (CK) to four integrate/hold circuits (I1to I4) which receive an incoming data signal, the integrate/hold circuits providing an error signal to the VCO (18) for adjusting the phase thereof to that of the incoming data signal, the integrate/hold circuits being sequenced by logic (10) to provide within each period of the clock signal three functions: (1) an integration of the incoming data signal in every bit period in which a voltage transition occurs, (2) a holding of the integrated value within a subsequent bit period or periods, and (3) a resetting of the integrated value following the next voltage transition in the incoming data signal, whereby the held integrated value, whose magnitude is dependent of the phase of the clock signal relative to the phase of the incoming data signal, provides said error signal.

Abstract: A television receiver is provided comprising a variable frequency local oscillator and frequency synthesizer control means for controlling the frequency of the variable frequency local oscillator in accordance with the setting of variable divider means for effecting channel or frequency tuning of said receiver, the frequency synthesis control means comprising first divider means operable on the output of the variable frequency local oscillator, the first divider means being set to one of a plurality of division ratios under the control of fine tuning means associated therewith, variable divider means operable on the output of the first divider means, and phase/frequency comparator means for comparing the output of the variable divider means with a reference frequency and for affording a control signal to the variable frequency local oscillator for controlling its frequency.