Abstract: This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.

Abstract: A semiconductor device wherein the layer of highly doped p-type material typically found in devices of the prior art is replaced with a layer of doped n-type material, having a doping concentration of between 1×1018 cm−3 and less than 1×1019 cm−3, and a thin layer of doped p type material thus facilitating low resistance contact, transparency to radiation produced by the device and confinement with low loss of radiation produced by laser devices.

Abstract: A semiconductor device wherein the layer of highly doped p-type material typically found in devices of the prior art is replaced with a layer of doped n-type material, having a doping concentration of between 1.times.10.sup.18 cm.sup.-3 and less than 1.times.10.sup.19 cm.sup.-3, and a thin layer of doped p type material thus facilitating low resistance contact, transparency to radiation produced by the device and confinement with low loss of radiation produced by laser devices.

Abstract: A low resistance contact for p-type GaAs is provided by Pd/Zn/Pd/Au structure 1. The contact is suitable for device substrates having carrier concentrations in the range of about 10.sup.18 to about 10.sup.20 cm.sup.-3. The ohmic contact has a Pd layer of depth 3 nm to 15 nm, a Zn layer with a depth of between 5 nm and 40 nm, a second Pd layer with a depth greater than about 50 nm and an Au layer with a depth greater than about 300 nm. A preferred construction (1) is 5 nm/10 nm/100 nm/400 nm of Pd/Zn/Pd/Au. The ohmic contact deposition must be followed by annealing, with preferred annealing carried out at a temperature of about 200.degree. C. Annealing times are dependent upon annealing temperature, with a typical minimum annealing times of greater than 5 minutes at annealing temperatures of about 200.degree. C.