Patents by Inventor Graham R. Wolstenholme
Graham R. Wolstenholme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250038109Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: ApplicationFiled: October 15, 2024Publication date: January 30, 2025Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 12125786Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: August 11, 2022Date of Patent: October 22, 2024Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Publication number: 20220384341Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: ApplicationFiled: August 11, 2022Publication date: December 1, 2022Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 11430734Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: December 28, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Publication number: 20220230960Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
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Patent number: 11393716Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: July 31, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 11302634Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.Type: GrantFiled: February 13, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
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Publication number: 20210257298Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
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Publication number: 20210151375Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: ApplicationFiled: December 28, 2020Publication date: May 20, 2021Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 10879175Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: May 7, 2019Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Publication number: 20200365452Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 10748811Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: April 8, 2019Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20190259703Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Publication number: 20190237362Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 10290581Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: March 9, 2018Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 10269626Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: January 10, 2018Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Publication number: 20180204799Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: ApplicationFiled: March 9, 2018Publication date: July 19, 2018Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Publication number: 20180130700Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: ApplicationFiled: January 10, 2018Publication date: May 10, 2018Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
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Patent number: 9941209Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: March 11, 2016Date of Patent: April 10, 2018Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 9870941Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.Type: GrantFiled: November 22, 2016Date of Patent: January 16, 2018Assignee: Micron Technology, Inc.Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda