Abstract: A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.

Abstract: A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.

Abstract: The invention relates to a circuit array for operating a liquid-crystal display in the time-division multiplexing mode, the display having at least one backplane and several segments. The circuit array includes a microprocessor having a first pulse generator, a shift register array storing data signals supplied to the circuit array, this shift register array having a number of stages corresponding to the number of segments, and driving stages which generate segment pulse sequences for the segments in accordance with the supplied data signals. In accordance with the invention, the microprocessor supplies the data signals to the shift register array via a first interface, the shift register array being designed as a cyclic shift register with each register point of the shift register array being clearly allocated to a segment. In addition, the microprocessor supplies control data, particularly data determining the time multiplexing rate, to a second interface having a decoder.