Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH peripheral circuitry area. At least some of the FLASH peripheral circuitry area spaced trench isolation regions have maximum depths which are greater than first and second maximum depths of trench isolation regions formed within array area.

Abstract: The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

Abstract: The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.

Abstract: Methods and devices are disclosed utilizing a polysilicon wings or ears in a stacked gate region. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and at least one polysilicon wing. The substrate has at least one semiconductor layer. The at least one trench is formed in the substrate and filled with an oxide. The oxide layer is formed over the substrate and the trench. The at least one floating gate layer is formed over the oxide layer. The at least one polysilicon wing is formed adjacent to vertical edges of the at least one floating gate layer and over the oxide layer. The present invention includes polysilicon wings or ears which can increase the capacitive coupling of memory cells in memory devices in which they are used. Generally, the polysilicon wings or ears are placed proximate to the floating gate of a memory cell. Thus, the present invention may allow for further reducing or scaling the size of memory cells and devices.

Abstract: In one implementation, a method of forming an array of FLASH memory includes forming a plurality of lines of floating gates extending from a memory array area to a peripheral circuitry area over a semiconductor substrate. In a common masking step, discrete openings are formed over a) at least some of the lines of floating gates in the peripheral circuitry area, and b) floating gate source area in multiple lines along at least portions of the lines of floating gates within the memory array area. In one implementation, a line of floating gates is formed over a semiconductor substrate. A conductive line different from the line of floating gates is formed over the semiconductor substrate. In a common masking step, discrete openings are formed to a) at least one of the conductive line and the line of floating gates, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates.

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates.

Abstract: In one implementation, a method of forming an array of FLASH memory includes forming a plurality of lines of floating gates extending from a memory array area to a peripheral circuitry area over a semiconductor substrate. In a common masking step, discrete openings are formed over a) at least some of the lines of floating gates in the peripheral circuitry area, and b) floating gate source area in multiple lines along at least portions of the lines of floating gates within the memory array area. In one implementation, a line of floating gates is formed over a semiconductor substrate. A conductive line different from the line of floating gates is formed over the semiconductor substrate. In a common masking step, discrete openings are formed to a) at least one of the conductive line and the line of floating gates, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates.

Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.

Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.