Patents by Inventor Grant A. Crawford

Grant A. Crawford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SIMPLIFIED BIOSAMPLE PROCESSING FOR LC-MS/MS
    Publication number: 20240159771
    Abstract: Disclosed are methods and systems using liquid chromatography/tandem mass spectrometry (LC-MS/MS) for the analysis of endogenous biomarkers isolated from biological samples. In certain embodiments, the samples comprise dried body fluids such as dried plasma.
    Type: Application
    Filed: September 29, 2023
    Publication date: May 16, 2024
    Applicant: Laboratory Corporation of America Holdings
    Inventors: Christopher Michael Shuford, Russell Philip Grant, Meghan Norris Bradley, Patricia Louise Miller Holland, Michael Levandoski, Matthew Lee Francis Crawford, Bradley Collier
  • Stimuli Responsive Microsphere Composites
    Publication number: 20200025747
    Abstract: An event detection composite in embodiments of the present invention may have one or more of the following features: (a) a plurality of solid and/or hollow and/or porous-wall microspheres, (b) a functional material disposed on or within the plurality of microspheres, wherein the functional material can have unique optical, electrical, magnetic, thermal, or chemical properties, where these properties can be realized upon the plurality of microspheres being exposed to a physical, optical, electrical, magnetic, thermal or chemical stimuli, and (c) a host matrix containing the plurality of microspheres.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 23, 2020
    Applicants: South Dakota Board of Regents, Applied Research Center
    Inventors: Grant A. Crawford, George G. Wicks, Forest Thompson
  • Misalignment correction for embedded microelectronic die applications
    Patent number: 9266723
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Grant A. Crawford, Islam Salama
  • MISALIGNMENT CORRECTION FOR EMBEDDED MICROELECTRONIC DIE APPLICATIONS
    Publication number: 20130119046
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 16, 2013
    Inventors: Grant A. Crawford, Islam Salama
  • Misalignment correction for embedded microelectronic die applications
    Patent number: 8372666
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Grant A. Crawford, Islam Salama
  • MISALIGNMENT CORRECTION FOR EMBEDDED MICROELECTRONIC DIE APPLICATIONS
    Publication number: 20120009738
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 12, 2012
    Inventors: Grant A. Crawford, Islam Salama