Patents by Inventor Grant Andrew Ellis

Grant Andrew Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7852153
    Abstract: A post-distortion method for cascading amplifier stages in a two-stage microwave power amplifier and a dynamic biasing method using back-end processing for correcting nonlinearity in the power amplifier output. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. The amplitude and phase responses of the two stages compensate another to yield a more linear overall gain for the overall power amplifier. The dynamic biasing scheme modulates the source to drain voltages of the transistors used in the amplifier stages based on the harmonics in amplifier output in order to minimize the harmonics and correct non-linearity in the output.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: December 14, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Grant Andrew Ellis, Miroslav Micovic, Keh-Chung Wang, JeongSun Moon
  • Patent number: 7477102
    Abstract: A post-distortion method for cascading amplifier stages in a two-stage microwave power amplifier and a dynamic biasing method using back-end processing for correcting nonlinearity in the power amplifier output. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. The amplitude and phase responses of the two stages compensate another to yield a more linear overall gain for the overall power amplifier. The dynamic biasing scheme modulates the source to drain voltages of the transistors used in the amplifier stages based on the harmonics in amplifier output in order to minimize the harmonics and correct non-linearity in the output.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: January 13, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Grant Andrew Ellis, Miroslav Micovic, Keh-Chung Wang, JeongSun Moon
  • Patent number: 7215221
    Abstract: A compact amplifier output bias circuit is used as a broadband harmonic termination. The bias circuit is adapted as a harmonic termination circuit to produce an effective low impedance or act as a load at the signal harmonic frequencies while having the capability of supplying DC power to the amplifier stage, optionally, if needed. A pi network is coupled to an active device output and provides a low impedance at frequency bands above a frequency band of operation while allowing DC bias to be appliable to the active device output.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: May 8, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Grant Andrew Ellis, Jeong-Sun Moon, Ara K. Kurdoghlian
  • Patent number: 6744409
    Abstract: A planar inverted-F antenna (PIFA) to facilitate communications within a plurality of frequency bands is disclosed. The top plate of the PIFA is placed at a predetermined height above a ground plane and shorting pins are placed in contact between the top plate and the ground plane. The feed pin is placed a predetermined distance away from each of the shorting pins within the interior area of the top plate. The shorting pins provide the ability to tune the PIFA to achieve either class-F or inverse class-F impedances over a wide range of frequencies. Also disclosed is an offset top loaded monopole (TLM) in which the feed pin connected to the top plate is offset from the centre of the top plate to provide a desired impedance.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 1, 2004
    Assignee: National University of Singapore
    Inventors: Grant Andrew Ellis, Saxon Sean Ian Liw
  • Publication number: 20030122716
    Abstract: A planar inverted-F antenna (PIFA) to facilitate communications within a plurality of frequency bands is disclosed. The top plate of the PIFA is placed at a predetermined height above a ground plane and shorting pins are placed in contact between the top plate and the ground plane. The feed pin is placed a predetermined distance away from each of the shorting pins within the interior area of the top plate. The shorting pins provide the ability to tune the PIFA to achieve either class-F or inverse class-F impedances over a wide range of frequencies. Also disclosed is an offset top loaded monopole (TLM) in which the feed pin connected to the top plate is offset from the centre of the top plate to provide a desired impedance.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventors: Grant Andrew Ellis, Saxon Sean Ian Liw