Abstract: A method and system for expanding the number of memory modules that can be coupled to a motherboard such as a server blade is presented. A stack of multiple Dual In-line Memory Modules (DIMMs) is formed using novel double-connector-edge DIMMs, which each have connector pins on their opposite edges. Alternatively, the double-connector-edge DIMM is used to couple the motherboard to a memory expansion card that has multiple single-edge pinned DIMMs coupled in a “daisy-chain.

Abstract: A heatpipe for cooling an integrated circuit. The heatpipe includes a pipe and radial fins that are formed by extruding a single piece of material, such as heat conducting metal. Each of the radial fins extends away from the pipe and runs (preferably) the length of the pipe. Each radial fin has normally oriented subfins that provide additional heat convection surface areas to the radial fins. Within the pipe are interior fins, also formed during the material extrusion process. The interior fins provide additional conduction cooling to a heat transferring fluid circulating within the pipe.

Abstract: A structure for cooling an electronic component includes a heat sink attached to the component, an inner air duct extending into a central portion of the heat sink, and an outer air duct extending into an outer portion of the heat sink. In inner fan, within the inner air duct, moves air in one direction, while an outer fan, in the outer air duct, moves air in the other direction. The fans may be built as separate rotors, or as separate portions of a single rotor.

Abstract: A daughter card includes a number of circuit modules generating heat and a spring member transmitting the heat to a thermal bus extending along a circuit board adjacent to one side or to each side of a connector to which the daughter card is releasably attached. One or more contact surfaces of the spring member releasably contact one or more mating surfaces of a thermal bus at a side of the connector or at both sides of the connector. A heat pipe may additionally be used to direct heat from the thermal bus to a heat absorber.

Abstract: A heat sink having graduated lengths of fins, with the tallest fins being in the center of the heat sink to provide maximum heat removal from a mated integrated circuit (IC) chip. Dual fans impinge air against the fins, and particularly the tallest fins, to provide a highly efficient system for heat removal from the IC chip. By reducing the size of the lateral fins, additional space is made available for the dual fans. The use of the dual fans allows the fans to run at a lower speed that a single fan, thus reducing an overall fan acoustic level. Furthermore, the dual fans allow for a backup fan system if one of the fans should fail.

Abstract: A heat sink having an air flow director on each of multiple fins attached to a heat sink base. The air flow directors direct most of the air flow from dual push-pull fans towards a midline and a geometric center of the heat sink base, which is above the hottest part of the integrated circuit (IC) package being cooled by the heat sink. The rest of the air flow from the push-pull fans impinges against the air flow directors, providing additional cooling to the fins.

Abstract: A heat sink having air flow directors on each of multiple fins attached to a heat sink base. The air flow directors direct air flow from dual fans towards a geometric center of the heat sink base, which is above the hottest part of the integrated circuit (IC) package being cooled by the heat sink. In one embodiment, a protrusion in the geometric center of the heat sink base provides additional cooling from air impingement, and also directs air towards the upper portions of the fins. The use of dual fans allows the fans to run at a lower speed than a single fan, thus reducing an overall fan acoustic level. Furthermore, the dual fans allow for a backup fan if one of the fans should fail.

Abstract: An apparatus for supporting I2C bus masters on a secondary side of an I2C mulitplexor is disclosed. An electronic system includes a primary serial bus, multiple secondary serial buses, an expander, multiple direction latches, a multiplexor, multiple busy detect circuits, and a to-from multiplexor circuit. The expander, which is coupled to the primary serial bus, includes multiple outputs that can be selectively activated. Each of the direction latches is coupled to a respective one of the outputs of the expander. The multiplexor, which is coupled to the direction latches, includes several outputs connected to the secondary serial buses such that the secondary serial buses can be selectively connected to the primary serial bus. Each of the busy detect circuits is coupled to a respective one of the outputs of the multiplexor. The busy detect circuits detects if there is a transaction occurring on one of the outputs of the multiplexor.

Abstract: An apparatus for supporting I2C bus masters on a secondary side of an I2C mulitplexor is disclosed. An electronic system includes a primary serial bus, multiple secondary serial buses, an expander, multiple direction latches, a multiplexor, multiple busy detect circuits, and a to-from multiplexor circuit. The expander, which is coupled to the primary serial bus, includes multiple outputs that can be selectively activated. Each of the direction latches is coupled to a respective one of the outputs of the expander. The multiplexor, which is coupled to the direction latches, includes several outputs connected to the secondary serial buses such that the secondary serial buses can be selectively connected to the primary serial bus. Each of the busy detect circuits is coupled to a respective one of the outputs of the multiplexor. The busy detect circuits detects if there is a transaction occurring on one of the outputs of the multiplexor.

Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.

Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.

Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.

Abstract: A computer or other electronic system includes a primary I2C bus and a plurality of secondary I2C buses that can be selectively coupled to the primary bus. The primary I2C bus is coupled to the input of an I/O expander, which has a unique address on the primary bus, and to the bus input of a bus switch. Each of the secondary I2C buses is coupled to a unique one of the bus outputs of the bus switch, which are controlled by a plurality on control inputs. Activating a selected control input of the bus switch couples the primary I2C bus to the corresponding secondary I2C bus. A controller addresses the I/O expander and then transmits a unique data byte that activates a selected output of the expander. Each of the outputs of the I/O expander is coupled to a unique control input of the bus switch through a delay circuit.