Abstract: Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously.

Abstract: Apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect, the invention relates to a PMIC having an internal non-volatile memory (NVM) for storing boot settings for the PMIC. The PMIC also has control circuitry for detecting whether a source of boot settings is available, such as an NVM external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry for automatically programming boot settings from an external source into the internal NVM.

Abstract: An audio device is provided that is arranged for communication of data and signalling with a controller, signalling from the device to the controller being made in discrete time slots, the device comprising: a plurality of nodes, each assigned a priority value and each having one or more unsolicited response sources capable of generating an unsolicited response for transmission to the controller, wherein unsolicited responses generated from a particular node are assigned the priority value of that node; and unsolicited response management means operable to hold unsolicited responses generated by the plurality of nodes that are awaiting transmission to the controller, wherein when two or more unsolicited responses are awaiting transmission to the controller in the unsolicited response management means, the device is arranged to transmit the unsolicited response with the highest assigned priority value first, in the next free time slot.

Abstract: Apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect, the invention relates to a PMIC having an internal non-volatile memory (NVM) for storing boot settings for the PMIC. The PMIC also has control circuitry for detecting whether a source of boot settings is available, such as an NVM external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry for automatically programming boot settings from an external source into the internal NVM.

Abstract: Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously.

Abstract: An integrated circuit combination, comprising first and second integrated circuit dies with respective first and second control register banks, and a path for external control data, within said combination, coupling a first data interface on said first die, which receives the external control data, to the first and second control register banks.