Patents by Inventor Grant S. Huglin

Grant S. Huglin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process of forming a semiconductor assembly having a contact structure and contact liner
    Patent number: 7524756
    Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: April 28, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Grant S. Huglin, Robert J. Burke, Sanh D. Tang
  • Method of making vertical transistor structures having vertical-surrounding-gates with self-aligned features
    Patent number: 7488651
    Abstract: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Grant S. Huglin
  • Vertical transistor structures having vertical-surrounding-gates with self-aligned features
    Patent number: 7242057
    Abstract: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: July 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Grant S. Huglin
  • Contact structure and contact liner process
    Patent number: 7170174
    Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: January 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Grant S. Huglin, Robert J. Burke, Sanh D. Tang