Abstract: A differential amplifier is disclosed with harmonic terminations. The differential amplifier has a first transistor having a first emitter coupled to a fixed voltage node, a first base, and a first collector. A second transistor has a second emitter coupled to the fixed voltage node, a second base, and a second collector. A first capacitor and a first inductor are coupled in series between the first collector and a virtual ground node. A second inductor and a second capacitor are coupled in series between the second collector and the virtual ground node, and a third inductor is coupled between the virtual ground node and the fixed voltage node. The first and second capacitors and first, second, and third inductors have capacitances and inductances, respectively, that are sized to realize second and third harmonic traps for a radio frequency signal being amplified by the differential amplifier.

Abstract: A power amplifier system is disclosed having a first stage amplifier that includes a first supply terminal, a first input, and a first output. A second stage amplifier has a second supply terminal, a second input, and a second output. A first stage bias circuitry has a bias output coupled to a bias input of the first stage amplifier and a bias control input. Absolute maximum ratings protection circuitry has a voltage monitoring input coupled to the second supply terminal and a bias control output coupled to the bias control input, wherein the absolute maximum ratings protection circuitry is configured to reduce the bias of the first stage amplifier through the bias control output based upon voltage monitored at the voltage monitoring input exceeding a predetermined voltage level. Additional absolute maximum ratings protection circuitry reduces the bias of the first stage amplifier if first stage amplifier supply voltage is excessive.

Abstract: A circuit having a substrate, a generator with a field effect transistor (FET) portion and a heterojunction bipolar transistor (HBT) portion integrated in the substrate, a voltage-to-voltage conveyor integrated in the substrate, a bias circuit, and a power amplifier is disclosed.

Abstract: Embodiments of circuits, systems, and methods relating to a voltage regulator circuit are disclosed. In particular, in accordance with some embodiments, a voltage regulator having a field effect transistor (FET) portion and a heterojunction bipolar transistor (HBT) portion integrated into a common substrate is provided. Other embodiments may be described and claimed.

Abstract: A method and apparatus for biasing an amplifying device whereby the bias current tracks the input power or the power level of a control signal to thereby efficiently match the bias current with needs of the amplifying device. This method and apparatus overcomes the drawbacks of the prior art by biasing, not for maximum output power, but for the power level of the input signal or the control signal. In one embodiment a current conditioner operates in connection with the self adjusting biasing circuit to scale or adjust, potentially on an exponential basis, the biasing current for one or more amplifier stages. A cancellation current source may be configured within the bias circuit to cancel unneeded current to further minimize current consumption.

Abstract: A method and apparatus for biasing an amplifying device whereby the bias current tracks the input power or the power level of a control signal to thereby efficiently match the bias current with needs of the amplifying device. This method and apparatus overcomes the drawbacks of the prior art by biasing, not for maximum output power, but for the power level of the input signal or the control signal. In one embodiment a current conditioner operates in connection with the self adjusting biasing circuit to scale or adjust, potentially on an exponential basis, the biasing current for one or more amplifier stages. A cancellation current source may be configured within the bias circuit to cancel unneeded current to further minimize current consumption.

Abstract: According to an exemplary embodiment, a circuit arrangement includes a multi-mode bias circuit having a control voltage input, a mode control input for selecting between a linear mode and a saturation mode, and a bias output. The circuit arrangement further includes an amplifier having a bias input connected to the bias output of the multi-mode bias circuit, the amplifier having an RF input and an RF output. The multi-mode bias circuit causes the amplifier RF output power to be proportional to the RF input power when the mode control input selects the linear mode. Conversely, the multi-mode bias circuit causes the amplifier RF output power to be determined by the voltage at the control voltage input when the mode control input selects the saturation mode.