Abstract: The invention relates to a device, system, and method for expanding the memory capacity of a memory module. A control unit and memory bank switch are mounted on a memory module to selectively control write and/or read operations to/from memory devices communicatively coupled to the memory bank switch. By selectively routing data to and from the memory devices, a plurality of memory devices may appear as a single memory device to the operating system. That is, the invention expands the addressable memory banks on a module by making two smaller-capacity memory devices emulate a single higher-capacity memory device.

Abstract: A glitch suppression circuit has a read pointer and a write pointer that track memory locations. A comparator compares the read pointer and the write pointer and provides a compare signal indicative of a particular memory condition. The glitch suppression circuit includes an offset read pointer and an offset write pointer that track memory locations. An offset comparator compares the read pointer and the write pointer and provides an offset compare signal indicative of the particular memory condition. A timing signal controls a multiplexer for selecting either the compare signal or the offset compare signal and sets a logic flag. The setting of the logic flag may be synchronized to a timing signal.

Abstract: A glitch suppression circuit has a read pointer and a write pointer that track memory locations. A comparator compares the read pointer and the write pointer and provides a compare signal indicative of a particular memory condition. The glitch suppression circuit includes an offset read pointer and an offset write pointer that track memory locations. An offset comparator compares the read pointer and the write pointer and provides an offset compare signal indicative of the particular memory condition. A timing signal controls a multiplexer for selecting either the compare signal or the offset compare signal and sets a logic flag. The setting of the logic flag may be synchronized to a timing signal.