Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: A computational method for constructing a synthetic peptide sequence is disclosed. The method of the present invention includes the steps of (i) identifying a candidate sequence building block set comprising candidate sequence building blocks from a base set comprising known functional peptide sequences and optionally known non-functional peptide sequences; (ii) selecting a qualified sequence building block set comprising qualified sequence building blocks from said candidate sequence building block set; said qualified sequence building blocks satisfying a threshold requirement and (iii) assembling said qualified sequence building blocks to generate a synthetic peptide sequence. A synthetic peptide sequence and a functional synthetic peptide are also described.

Abstract: An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.

Abstract: An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.

Abstract: In some embodiments, a system is provided that includes an edge computing device and at least one camera configured to obtain image data depicting at least a portion of an operations area. The edge computing device includes a non-transitory computer-readable medium that has a model data store and computer-executable instructions stored thereon. The instructions cause the edge computing device to perform actions including receiving at least one image from the at least one camera; processing the at least one image using at least one machine learning model stored in the model data store to determine at least one environmental state within the operations area; and controlling a device based on the determined at least one environmental state. The machine learning model is trained by a model management computing system that obtains training data via low-bandwidth connections to edge computing devices.

Abstract: A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.

Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.

Abstract: A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.

Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: A control system for a double-acting air cylinder of an agricultural implement includes a valve assembly configured to control a base end air pressure and a rod end air pressure of the double-acting air cylinder. The control system also includes a controller communicatively coupled to the valve assembly. The controller is configured to determine a target base end air pressure and a target rod end air pressure based on a target force of the double-acting air cylinder and a target damping factor of the double-acting air cylinder. The controller is also configured to control the valve assembly such that a first difference between the base end air pressure and the target base end air pressure is less than a first threshold value and a second difference between the rod end air pressure and the target rod end air pressure is less than a second threshold value.

Abstract: A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

Abstract: An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Abstract: This disclosure relates to the processing of data streams. More specifically, application of particular protocols to a stream and a detection analysis facilitate a selective, reliable and efficient transmission of pertinent stream data to destination addresses.

Abstract: Exemplary embodiments relate to improvements in robotic systems to reduce biological or chemical harborage points on the systems. For example, in exemplary embodiments, robotic actuators, hubs, or entire robotic systems may be configured to allow crevices along joints or near fasteners to be reduced or eliminated, hard corners to be replaced with rounded edges, certain components or harborage points to be eliminated, shapes to be reconfigured to be smoother or flat, and/or or surfaces to be reconfigurable for simpler cleaning.

Abstract: An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Abstract: A monitoring system for an agricultural implement includes a sensor configured to output a sensor signal indicative of a position of at least one scraper of the agricultural implement relative to a surface of at least one respective disc. The at least one scraper is configured to engage the surface of the at least one respective disc to remove accumulated soil from the surface of the at least one respective disc. The monitoring system also includes a controller communicatively coupled to the sensor. The controller is configured to determine an amount of wear on the at least one scraper based on the position of the at least one scraper relative to the surface of the at least one respective disc, and the controller is configured to output a wear signal indicative of the amount of wear on the at least one scraper.

Abstract: A mounting assembly for an agricultural product meter includes an upper mount configured to support at least a portion of a weight of the agricultural product meter. The upper mount is configured to couple to a support structure. The mounting assembly also includes a pin configured to engage the agricultural product meter via movement of the pin along a longitudinal axis of the pin. In addition, the mounting assembly includes a lower mount configured to selectively receive the pin via movement of the pin along the longitudinal axis of the pin. The lower mount is configured to couple to the support structure, and the pin is configured to block movement of the agricultural product meter away from the support structure while the pin is engaged with the agricultural product meter and the lower mount.

Abstract: A method and/or apparatus using programmable device for parallel processing logic operations is disclosed. The apparatus, such as a semiconductor integrated circuit die, includes an input memory, a processing unit, and an accelerator. The input memory is used to buffer input signals from an external component. The processing unit, such as a microcontroller, retrieves the input signals from the input memory and generates pre-processed data in accordance with the input signals. The first configured circuit containing configurable logic blocks (“LBs”) of a field programmable logic array (“FPGA”), in one embodiment, is programmed as an accelerator to perform one or more neural networking functions. For example, the accelerator is able to process a set of convolutional operation in response to at least a portion of the pre-processed data offloaded from the processing unit for identifying a result or reference.

Abstract: A crimping tool, for attaching at least one wire to a connector, includes a housing, a first handle coupled to the housing, and a second handle coupled to the housing and movable relative to the first handle. The crimping tool also includes a working head coupled to the housing opposite the first and second handles. The working head includes an upper wall, an end wall, and a gap defined between the upper wall and the end wall. The crimping tool also includes a punch assembly slidable along the working head toward the end wall in response to movement of the second handle toward the first handle. The punch assembly is visible through the gap as the punch assembly slides toward the end wall.