Patents by Inventor Grant Villavicencio

Grant Villavicencio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100327461
    Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: Vertical Circuits, Inc.
    Inventors: Reynaldo Co, Grant Villavicencio, Jeffrey S. Leal, Simon J.S. McElrea
  • Publication number: 20090315174
    Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.
    Type: Application
    Filed: November 25, 2008
    Publication date: December 24, 2009
    Applicant: VERTICAL CIRCUITS, INC.
    Inventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio
  • Publication number: 20080315434
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J.S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu