Abstract: An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

Abstract: A probe assembly is provided and includes a probe card, an interposer body disposed on a surface of the probe card, probe pins arranged in a grouping and extending from the interposer body away from the probe card, each probe pin including an elongate element and a tip at a distal end of the elongate element, a mold supportable on the interposer body to fit around the grouping of the probe pins and non-conductive elastic material introduced into and cured within an interior region defined by the mold to surround at least the elongate element of each probe pin.

Abstract: A wafer test probe includes a pillar, a conductive line isolated from and extending through the pillar, a probe tip forming an opening, and a first conductive coating isolated from the pillar to coat the probe tip at least at the opening. The probe time includes blade features disposed in electrical contact with the conductive line via the first conductive coating. The blade features terminate at the opening and are configured to conductively penetrate a solder bump. A second conductive coating is disposed over the first conductive coating to coat the blade features.

Abstract: An IC device test probe has one or more clusters of a plurality of tapered probe tips that taper upon a taper plane that is orthogonal to a seating direction or force vector of the IC device test probe toward the IC device. Each of the plurality of tapered probe tips is seated against one contact of the IC device. In this manner, the IC device test probe is seated against multiple contacts and may therefore apply test signal(s) to these contacts serially, simultaneously, or the like. The IC device test probe allows the seating to small pitch IC devices and associated testing thereof. This allows for electrical characterization of the IC device by the same test signal(s) through the IC device test probe and ultimately through multiple contacts. The forces associated with seating the IC device test probe against the IC device contacts is effectively spread across multiple contacts.

Abstract: An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

Abstract: An IC device test probe has one or more clusters of a plurality of tapered probe tips that taper upon a taper plane that is orthogonal to a seating direction or force vector of the IC device test probe toward the IC device. Each of the plurality of tapered probe tips is seated against one contact of the IC device. In this manner, the IC device test probe is seated against multiple contacts and may therefore apply test signal(s) to these contacts serially, simultaneously, or the like. The IC device test probe allows the seating to small pitch IC devices and associated testing thereof. This allows for electrical characterization of the IC device by the same test signal(s) through the IC device test probe and ultimately through multiple contacts. The forces associated with seating the IC device test probe against the IC device contacts is effectively spread across multiple contacts.

Abstract: Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.

Abstract: Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.

Abstract: A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.

Abstract: A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.

Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: Embodiments herein describe structures of low-force wafer test probes and formation thereof. Structures of low-force wafer test probes and their formation via gray scale etch or electroplating is described. Structures are described that include a lower base structure on top of a substrate and an upper blade structure on top of the lower base structure. In various embodiments, a crown of a C4 bump is accommodated by one or both of: i) a cavity present in the lower base structure; and ii) a height of the upper blade structure. Processes for fabricating probe structures are described that include forming lower base structures upon a substrate and forming upper blade structures on top of the lower base structures. The upper blade structures include at least one blade. Each of the blade(s) include a cutting edge that points toward a center point within the probe structure.

Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage. Further, the method includes raising the test stage toward the test probe until an alignment feature of the test probe engages a first solder ball of the die, and fine aligning the die with reference to the test probe by continuing to raise the test stage until a second solder ball of the die fits into a test cup of the test probe.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: A method of treating a material on a probe is provided. The method includes the steps of immersing a probe tip into a first fluid, wherein the probe tip includes one or more oxidized metallic fragments on a surface of the probe tip; polarizing the probe tip, through a counter electrode, with a negative current to reduce the one or more oxidized metallic fragments to one or more substantially unoxidized metallic fragments; removing the probe tip from the first fluid; immersing the probe in a second fluid, wherein the second fluid is a complexer for the one or more substantially unoxidized metallic fragments; and polarizing the probe tip with a positive current, through the counter electrode, wherein the positive current oxidizes the one or more substantially unoxidized metallic fragments.

Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A semiconductor die is aligned to a test probe by placing the semiconductor die onto a flat upper surface of a test stage with solder balls of the die facing upward, fluidizing motion of the die with reference to the test stage by pulsing gas between the die and the upper surface of the test stage, and coarse aligning the die with reference to the test stage by moving the die until adjacent edges of the die contact corner guides that are disposed on the test stage.

Abstract: A method of treating a material on a probe is provided. The method includes the steps of immersing a probe tip into a first fluid, wherein the probe tip includes one or more oxidized metallic fragments on a surface of the probe tip; polarizing the probe tip, through a counter electrode, with a negative current to reduce the one or more oxidized metallic fragments to one or more substantially unoxidized metallic fragments; removing the probe tip from the first fluid; immersing the probe in a second fluid, wherein the second fluid is a complexer for the one or more substantially unoxidized metallic fragments; and polarizing the probe tip with a positive current, through the counter electrode, wherein the positive current oxidizes the one or more substantially unoxidized metallic fragments.