Patents by Inventor Grayce A. Hickman

Grayce A. Hickman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
    Patent number: 5356831
    Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.
    Type: Grant
    Filed: October 28, 1992
    Date of Patent: October 18, 1994
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Grayce A. Hickman
  • Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
    Patent number: 5164359
    Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.
    Type: Grant
    Filed: April 20, 1990
    Date of Patent: November 17, 1992
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Grayce A. Hickman
  • Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
    Patent number: 5159413
    Abstract: A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.
    Type: Grant
    Filed: December 11, 1990
    Date of Patent: October 27, 1992
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Grayce A. Hickman
  • Low temperature semiconductor bonding process with chemical vapor reaction
    Patent number: 5010036
    Abstract: A semiconductor chip (14) is bonded to a substrate (16) by a metallic molecular bond interface (28, 38, 30). The chip and the substrate are separated by a gap (18), and a metal-bearing gas is introduced in the gap. A thermal energy source (22) directs a focused energy beam (24) into the gap to thermally decompose the gas by chemical vapor reaction to deposit and grow metal to provide a metallic molecular bond interface filling the gap and bonding the chip to the substrate. In the preferred embodiment, one of the chip and substrate has a passband passing the wavelength of the focused beam to be transparent thereto such that the beam passes therethrough and into the gap and against the other of the chip and the substrate.
    Type: Grant
    Filed: April 20, 1990
    Date of Patent: April 23, 1991
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Grayce A. Hickman