Abstract: A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.

Abstract: A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.

Abstract: A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.

Abstract: A cascode current mirror circuit includes a cascode connected input stage (401) that operates to conduct an input current (400) in response to an input voltage of an input signal coupled to an effective transconductance of the cascode connected input stage (401). An input mirroring transistor (404) operates to control a mirror reference current (406) in response to the input voltage of the input signal. A diode connected transistor (409) coupled to a second control node of the cascode connected input stage (410) generates a control bias proportional to the mirror reference current (406) and to the input signal. A cascode connected output stage (411) has a first control node (413) coupled to the input signal and a second control node (414) coupled to the diode connected transistor (409) and the second control node (410) of the cascode connected input stage (401) for establishing an output current (415) that is substantially equivalent to the input current (400).

Abstract: A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).

Abstract: A current mirror (100) has an input stage (104) and an output stage (106), both preferably employing FET's. (Field Effect Transistors) An amplifier (102) equalizes drain-to-source voltages between FET's in the input and output stages to provide a higher output impedance. A resistance (R1), coupled in series with an FET in the output stage (106), provides degenerative feedback. A reference current generator (400) is constructed of two such current mirrors, one being the compliment of the other, to provide one or more stable reference currents. Loop gain of the reference current generator (400) is greater than one at start-up, but degenerative feedback reduces the loop gain to one at a predetermined stable operating point.

Abstract: A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

Abstract: A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.

Abstract: A complementary cascode push-pull amplifier circuit includes a bias generator, a complementary bias generator, a cascode input stage (416, 417), a cascode output stage (410, 411), a complementary cascode input stage (456,457), and a complementary cascode output stage (450,451). The bias generator is responsive to a first input signal (420) and generates a bias control voltage. The complementary bias generator is responsive to a second input (421) and generates a complementary bias control voltage. The cascode output stage (410, 411) and the complementary cascode output stage (450,451) each have an output coupled to a common output terminal (510) for generating a portion of an output current signal in response to the respective input signals (420, 421) and in response to the bias control voltage and the complementary bias control voltage being generated.

Abstract: A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.