Patents by Inventor Greg A Burd

Greg A Burd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8136005
    Abstract: A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 13, 2012
    Assignee: Marvell International Ltd.
    Inventors: Nersi Nazari, Zining Wu, Greg A Burd