Abstract: A memory unit is presented including a data array for storing data items (e.g., instructions and/or data) a hit circuit, and a miss circuit. The data items stored within the data array are accessed by multiple data access signals, wherein assertion of one of the data access signals indicates the presence of a requested data item within the data array. The hit circuit includes multiple driver cells coupled to two signal lines: a bit line and a bit′ line. Each driver cell receives a different one of the data access signals. When one of the data access signals is asserted, the receiving driver cell drives the bit line toward a first voltage level (e.g., VCC), and drives the bit′ line toward a second voltage level (e.g., VSS). The miss circuit is coupled to the bit and bit′ lines, and drives the bit line toward VSS.