Patents by Inventor Greg A. Dix

Greg A. Dix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495657
    Abstract: A process is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. An oxide cap is formed over the TFR film, which acts as a hardmask during a TFR etch of the TFR film to define a TFR element, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer. TFR edge spacers may be formed over lateral edges of the TFR element to insulate such TFR element edges. TFR contact openings are etched in the oxide cap over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 8, 2022
    Assignee: Microchip Technology Incorporated
    Inventors: Paul Fest, Jacob Williams, Josh Kaufman, Greg Dix
  • Publication number: 20210273037
    Abstract: A process is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. An oxide cap is formed over the TFR film, which acts as a hardmask during a TFR etch of the TFR film to define a TFR element, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer. TFR edge spacers may be formed over lateral edges of the TFR element to insulate such TFR element edges. TFR contact openings are etched in the oxide cap over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element.
    Type: Application
    Filed: October 15, 2020
    Publication date: September 2, 2021
    Applicant: Microchip Technology Incorporated
    Inventors: Paul Fest, Jacob Williams, Josh Kaufman, Greg Dix
  • Patent number: 10753964
    Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 25, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Philippe Deval
  • Patent number: 10326013
    Abstract: A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 18, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Publication number: 20190123654
    Abstract: A circuit arrangement for switched mode power conversion is disclosed, which circuit arrangement comprises at least an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device; a plurality of controllable switching devices; a first controllable voltage source, configured to provide a first control voltage to one or more of the plurality of controllable switching devices, and at least a second controllable voltage source, configured to provide a second control voltage to one or more of the plurality of controllable switching devices. To improve the efficiency of the circuit arrangement, the first and the second controllable voltage sources are configured to allow independent control of the first and second control voltages.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 25, 2019
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Joseph Depew
  • Publication number: 20190123196
    Abstract: An integrated circuit (IC) device may include a plurality of trench-type field-effect transistors (trench FETs). Each trench FET may include a poly gate trench formed in an epitaxy region, a poly gate formed in the poly gate trench, a front-side poly gate contact, and a lateral gate coupling element (e.g., a lateral “strap”) extending over or adjacent, and in contact with, at least one surface of the poly gate formed in the trench and electrically connecting the poly gate to the front-side poly gate contact. The lateral gate coupling element may be formed from a material having a higher electrical conductivity than the poly gate, e.g., tungsten or other metal. The lateral gate coupling element may be at least partially located in the poly gate trench.
    Type: Application
    Filed: July 25, 2018
    Publication date: April 25, 2019
    Applicant: Microchip Technology Incorporated
    Inventor: Greg Dix
  • Patent number: 10217810
    Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 26, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Randy Yach, Francesco Mazzilli
  • Publication number: 20180313874
    Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 1, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Philippe Deval
  • Publication number: 20180145171
    Abstract: An integrated circuit (IC) structure may include one or more trench-based semiconductor devices, e.g., field-effect transistors (trench FETs), having a front-side drain contact. Each semiconductor device may include an epitaxy layer, a doped source region in the epitaxy layer, a front-side source contact coupled to the source region, a poly gate formed in a trench in the epitaxy layer, and a front-side drain contact extending through the poly gate trench and isolated from the poly gate. The device may define a drift region from the poly gate/source region intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extends into an underlying bulk substrate or transition layer. The depth of the front-side drain contact may be selected to influence the breakdown voltage of the respective device. In addition, the front-side drain contacts may allow the IC structure to be flip-chip mounted or packaged.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 24, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Publication number: 20180145170
    Abstract: A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 24, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Patent number: 9812380
    Abstract: A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: November 7, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Roger Melcher, Harold Kline
  • Publication number: 20170162648
    Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.
    Type: Application
    Filed: November 9, 2016
    Publication date: June 8, 2017
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Randy Yach, Francesco Mazzilli
  • Patent number: 9634135
    Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 25, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg A. Dix, Dan Grimm
  • Publication number: 20160013121
    Abstract: A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.
    Type: Application
    Filed: March 30, 2015
    Publication date: January 14, 2016
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Roger Melcher, Harold Kline
  • Publication number: 20130228854
    Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.
    Type: Application
    Filed: February 27, 2013
    Publication date: September 5, 2013
    Applicant: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg A. Dix, Dan Grimm
  • Patent number: 7170136
    Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 30, 2007
    Assignee: Microchip Technology Incorporated
    Inventors: Randy L. Yach, Greg Dix
  • Publication number: 20060017109
    Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.
    Type: Application
    Filed: August 10, 2005
    Publication date: January 26, 2006
    Inventors: Randy Yach, Greg Dix
  • Patent number: 6987300
    Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: January 17, 2006
    Assignee: Microchip Technology Incorporated
    Inventors: Randy L. Yach, Greg Dix
  • Publication number: 20050212052
    Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 29, 2005
    Inventors: Randy Yach, Greg Dix