Abstract: Quality of service (QOS) may be improved within a wireless network by moving one or more wireless client devices from a present wireless channel to another channel in the network.

Abstract: A method is presented that may reduce the number of I/O transactions needed to transfer data between a host device and peripheral device over a parallel port. According to one embodiment, only two I/O transactions are needed to transfer a byte of data as opposed to the eight I/O transactions need in the IEEE 1284-1994 standard. During the two I/O transactions (e.g., transferring data from the host device to the peripheral device), the host device places the data on the data signal lines of the parallel port and toggles a signal on one of the control signal lines. In response, the peripheral device reads the data from the parallel port. Additional bytes can be sent by placing the data onto the port and toggling the signal on the same control signal line. Using this method, a data rate of approximately 4 Mega bits per second may be achieved.

Abstract: An apparatus for interfacing a memory with a bus in a computer system is described. The memory has a data path width which is different than the data path width of the bus. The apparatus comprises a first and a second buffer, a first and a second address generation circuit, and a control circuit. The first buffer is for storing a first portion and a second portion of a first data read from the memory during a read operation which are to be sent to the bus in parallel. The first address generation circuit is for receiving a first address from the bus during the read operation and generating a first memory address to address the memory for the first portion of the first data and a second memory address to address the memory for the second portion of the first data. The second buffer circuit is for storing a second data received from the bus during a write operation.

Abstract: A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing control (IOCHRDY) signal should be activated by an I/O mapped system resource. The present invention includes lost circuitry for determining whether a particular system resource operates best in a late IOCHRDY mode or an early IOCHRDY mode. The test logic will force the IOCHRDY signal to remain active for an extended period of time. By extending the deactivation time of the IOCHRDY signal far beyond the time at which the deactivation would normally occur, the responsiveness of a command strobe (IORD/IOWR) may be tested.

Abstract: A circuit and a related process are utilized in a computer system for testing and configuring the width of various portions of memory in a memory array. The circuit captures a state of a memory width control signal (MEMCS16) during a test and configuration cycle, retains the state of the MEMCS16 signal for various blocks of memory, and controls the state of the MEMCS16 signal when a memory access to a particular memory block is made. The circuit tests the state of the MEMCS16 signal for various blocks of the system memory map and thereafter configures a memory control register appropriately. The state of the MEMCS16 signal is retained by a latch when a particular 128K region is accessed and a valid address is present on the address lines. The output of the latch is provided as a processor-readable test result in a bit of a control/test register.