Abstract: An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.

Abstract: An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.

Abstract: Compression and decompression apparatus and methods for producing fixed-length compressed data blocks with variable-length compression are described. The compression system receives an N-bit word from a data block and determines the variable compression length for the word. A bit counter keeps track of the number of bits remaining and determines if sufficient bits have been used to ensure that the fixed-length compressed data block will be filled. If so, the compressed word is output. If not, prior to output the compressed word is padded with an appropriate number of bits, which may be null bits.

Abstract: An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit, insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.

Abstract: An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.

Abstract: An MPEG decoder in a high definition television receiver decodes and decompresses MPEG coded data to produce decompressed image pixel blocks, and includes a motion compensation network coupled to a frame memory to produce finally decoded pixel data for display. The decompressed MPEG data is recompressed by plural parallel recompressors prior to storage in frame memory. Each recompressor receives a datastream of interleaved pixel data, and predicts and compresses interleaved pixel values during each clock cycle, respectively. One of the recompressors is de-energized in a reduced data processing mode when pixel data is subsampled prior to recompression. Subsampled data is re-ordered prior to recompression. Multiple parallel decompressors coupled to the frame memory provide pixel data to the motion processing network. A control unit insures an uninterrupted interleaved data flow to the decompressors by repeating last valid data when source data is interrupted.

Abstract: A video processing device capable of minimizing clock cycles lost to overhead information includes an encoder for generating first and second groups of overhead bits. The first group includes a fixed number of overhead bits and the second group includes a variable number of overhead bits. A shift register receives pixel data from a data source, receives the second group of overhead bits from the encoder, and provides output of the pixel data and the second group of overhead bits. A multiplexer receives the pixel data and the second group of overhead bits from the shift register, receives the first group of overhead bits from the encoder, and provides output of the pixel data and the first and second groups of overhead bits which are then combined in an output register.

Abstract: A delay correction circuit includes a source of a clock signal and a source of a timing signal asynchronous with the clock signal. A timing signal detector is responsive to the clock signal and the timing signal, and is properly operative only when the timing signal is stable for a predetermined time period around the clock signal. A control circuit conditions utilization circuitry to operate after a delay time after the timing signal is detected. Adjusting circuitry conditions the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.

Abstract: A television receiver includes an MPEG decoder for providing decoded pixel blocks. Decoded pixels are recompressed prior to storage in frame memory. In the recompression process a reference first pixel is compressed as a function of a pixel block parameter. A reconstructed reference pixel value is used in a prediction network when reconstructing remaining pixels of the pixel block prior to display. A first pixel processor accurately compresses a reference pixel which prevents the propagation of a prediction error throughout the reconstructed block.

Abstract: An M-bit digital signal, the most significant bit (MSB) thereof and an integer K are added to produce a sum which is truncated by N least significant bits to provide a symmetrically rounded bit-reduced digital output signal. The MSB may be applied in true or complemented form to the adder for selecting wide or narrow rounding modes having different numbers of output zeros disposed about a point of symmetry for a given input signal change. Advantageously, undesirable direct current (DC) shifts due to least significant bit (LSB) reduction in digital video, audio or similar applications are prevented.