Abstract: Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

Abstract: Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

Abstract: An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.

Abstract: A fuel injector controller is disclosed. The fuel injector controller may determine respective values of a set of parameters of the engine; process, using a neural network, the respective values to determine a target fuel output of a fuel injector, wherein the neural network is configured to determine the target fuel output based on the set of parameters being an input layer of the neural network; determine, based on an output of the neural network, the target fuel output; and provide the determined target fuel output to the fuel injector to permit the fuel injector to inject fuel according to the target fuel output.

Abstract: A fuel injector controller is disclosed. The fuel injector controller may determine respective values of a set of parameters of the engine; process, using a neural network, the respective values to determine a target fuel output of a fuel injector, wherein the neural network is configured to determine the target fuel output based on the set of parameters being an input layer of the neural network; determine, based on an output of the neural network, the target fuel output; and provide the determined target fuel output to the fuel injector to permit the fuel injector to inject fuel according to the target fuel output.