Patents by Inventor Greg Burton

Greg Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5227316
    Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base region to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.
    Type: Grant
    Filed: August 12, 1991
    Date of Patent: July 13, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Madhukar Vora, Greg Burton, Ashok Kapoor
  • Patent number: 5061986
    Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base regions to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: October 29, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Madhukar Vora, Greg Burton, Ashok Kapoor
  • Patent number: 4539744
    Abstract: A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.
    Type: Grant
    Filed: February 3, 1983
    Date of Patent: September 10, 1985
    Assignee: Fairchild Camera & Instrument Corporation
    Inventor: Greg Burton