Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.

Abstract: A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.

Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract: A process of forming a wiring in a semiconductor interlayer dielectric, include simultaneously patterning a via and a slotted line in the interlayer diectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal.

Abstract: The present invention provides an improved semiconductor ridge waveguide laser structure having a plurality of layers including an N-InP buffer layer and an N-type InP substrate, a thin InGaAsP active layer 1100 Angstroms thickness, a P-InP graded layer, an optional etch stop layer, a P-InP cladding layer and a P+InGaAs. The ridge waveguide laser of the present invention demonstrates a very high reliability and the fabrication process therefor is high yield. The ridge waveguide laser of the present invention demonstrates very good high temperature behavior and the design suppresses higher order modes.

Abstract: A protection configuration for a semiconductor ridge waveguide laser structure is disclosed wherein layers of protective metal in the form of walls, is applied on each side of the ridge element of the ridged layer of the laser structure. The laser structure is then bonded to a mounting plate in a junction side down orientation by solder or a junction side up orientation by wire bonding. The metal layer may be composed of gold.