Patents by Inventor Greg Dermer

Greg Dermer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power delivery system in which VRM and CPU exchange power consumption measurements
    Patent number: 8694816
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: April 8, 2014
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Power Delivery System
    Publication number: 20090199033
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Application
    Filed: January 20, 2009
    Publication date: August 6, 2009
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Power delivery system in which power supply and load exchange power consumption measurements via digital bus
    Patent number: 7523337
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: April 21, 2009
    Assignee: Intel Corporation
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Power delivery system
    Publication number: 20060041763
    Abstract: A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 23, 2006
    Inventors: Shekhar Borkar, Tanay Karnik, Peter Hazucha, Gerhard Schrom, Greg Dermer
  • Method for initializing an array of configurable components
    Patent number: 5701420
    Abstract: A method for configuring a plurality of configurable components within a computer system. The method includes the step of asserting a RESET signal for all of the configurable components. The RESET signal is asserted by a diagnostic processor within the system. The components each respond with an ERROR # signal which provides an indication to the diagnostic processor that the component is in an inactive state. After a predetermined number of clock signals the diagnostic processor configures a first component, then a second component and so forth and so on, until all of the components are configured. After all of the components are configured, the diagnostic processor deasserts the RESET signal for the first component, then deasserts the RESET signal for the second component and so forth and so on, until all of the RESET signals have been deasserted. Each component deasserts the ERROR # signal upon the deassertion of the RESET signal.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: December 23, 1997
    Assignee: Intel Corporation
    Inventors: David J. Nedwek, Howard Wilson, Steve Nugent, Greg Dermer