Patents by Inventor Greg Dykema

Greg Dykema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12688148
    Abstract: System and method for optimizing data-transfer among multiple compute units in a data-parallel computing system. A topological communications configurator (TCC) determines a connections-optimized configuration of processors associated with compute nodes of the computing system. The processors can execute dataflow workers of an application and form intranodal segments of an internodal interconnection topology coupling the intranodal segments. The TCC determines the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric.
    Type: Grant
    Filed: August 5, 2024
    Date of Patent: July 21, 2026
    Assignee: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Aarti Lalwani
  • Publication number: 20260140920
    Abstract: A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application.
    Type: Application
    Filed: September 30, 2025
    Publication date: May 21, 2026
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg DYKEMA, Maran WILSON, Guoyao FENG, Kuan ZHOU, Tianyu SUN, Taylor LEE, Kin Hing LEUNG, Arnav GOEL, Conrad Alexander TURLIK, Milad SHARIF
  • Publication number: 20260030174
    Abstract: A coarse-grained reconfigurable processor (CGRP) system. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first coarse-grained reconfigurable processor that is coupled to a first memory, a network interface including an external direct memory access (DMA) engine coupled to the first memory, and a work queue associated with the external DMA engine.
    Type: Application
    Filed: September 30, 2025
    Publication date: January 29, 2026
    Applicant: SambaNova Systems, Inc.
    Inventors: Amitabh MENON, Greg DYKEMA
  • Patent number: 12450193
    Abstract: A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: October 21, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing Leung, Arnav Goel, Conrad Turlik, Milad Sharif
  • Patent number: 12450167
    Abstract: A coarse-grained reconfigurable processor (CGRP) system for implementing data-parallel training of a neural network is presented. The CGRP system includes a set of coarse-grained reconfigurable units (CGRUs) in a first CGRP configured to implement at least a portion of the neural network, to determine first and second gradients, respectively, of first and second model parameters based on a batch of training data, and to store the first and second gradients in a memory, a network interface including an external direct memory access (DMA) engine coupled between the memory and a network, and a work queue associated with the external DMA engine, wherein completion of determining the first gradient triggers a first work queue entry of the work queue that directs the external DMA engine to transfer the first gradient from the memory over the network to another memory coupled to a second CGRP for a gradient reduction operation.
    Type: Grant
    Filed: July 17, 2024
    Date of Patent: October 21, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Amitabh Menon, Greg Dykema
  • Publication number: 20240394218
    Abstract: System and method for optimizing data-transfer among multiple compute units in a data-parallel computing system. A topological communications configurator (TCC) determines a connections-optimized configuration of processors associated with compute nodes of the computing system. The processors can execute dataflow workers of an application and form intranodal segments of an internodal interconnection topology coupling the intranodal segments. The TCC determines the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg DYKEMA, Aarti LALWANI
  • Publication number: 20240273057
    Abstract: A host system for executing an application on first and/or second reconfigurable processors is presented. The host system is operatively coupled to the first and second reconfigurable processors, whereby the first reconfigurable processors have a first architecture, and the second reconfigurable processors have a second architecture that is different than the first architecture. The host system allocates reconfigurable processors of the first and/or second reconfigurable processors for executing the application and includes an auto-discovery module that is configured to determine whether the allocated reconfigurable processors include at least one of the first reconfigurable processors.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 15, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg DYKEMA, Maran WILSON, Guoyao FENG, Kuan ZHOU, Tianyu SUN, Taylor LEE, Kin Hing LEUNG, Arnav GOEL, Conrad Alexander TURLIK, Milad SHARIF
  • Patent number: 12056085
    Abstract: A computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system. Processors included in the compute nodes can execute compute workers of an application of the system and can form intranodal segments of an internodal interconnection topology communicatively coupling the intranodal segments. The intranodal segments can be interconnected via an internodal interconnections fabric. The TCC can determine the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric. The computing system can comprise the TCC and can comprise a data-parallel computing system.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: August 6, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Aarti Lalwani
  • Publication number: 20240231903
    Abstract: In a computer-implemented method a Dynamic Transfer Engine (DTE) included in a computing system receives a dynamic stimulus associated with transfer of stage data during execution of a dataflow application by the system. The DTE determines, based on source and destination devices of the transfer, a transfer method and a transfer channel to transfer the stage data between memories coupled to the source and destination devices. The DTE acquires, hardware resources of the computing system to transfer the stage using the channel and, initiates the transfer. A computer program product can cause one or more processors to perform the method. A computing system can comprise source and destination processors and memories, hardware channels to transfer data between the memories, a resource manager, and a DTE configured to perform the method.
    Type: Application
    Filed: March 23, 2024
    Publication date: July 11, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Qi ZHENG, Arnav GOEL, Conrad Alexander TURLIK, Guoyao FENG, Joshua Earle POLZIN, Fansheng CHENG, Ravinder KUMAR, Greg DYKEMA, Subhra MAZUMDAR, Milad SHARIF, Jiayu BAI, Neal SANGHVI, Arjun SABNIS, Letao CHEN
  • Patent number: 11983141
    Abstract: A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: May 14, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing Leung, Arnav Goel, Conrad Turlik, Milad Sharif
  • Publication number: 20230259823
    Abstract: In a method an orchestrator of a computing system determines that results of Machine Learning model computations are available and dispatches a worker to perform model computations that include computing gradients of the results. The orchestrator determines that a set of gradients of the results is available and dispatches a gradient worker to compute a sum of the gradients. The orchestrator determines that a second set of gradients of the results is available and dispatches a second gradient worker to compute a sum of the second set of gradients. The orchestrator determines that the sums of the first and second gradients are available and dispatches a third gradient worker to compute synchronized gradients. The gradient workers compute the sums and synchronized gradients concurrent with training workers computing additional model computations results and/or gradients. A computer program product can include the method and a computing system can include the orchestrator.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 17, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg DYKEMA, Fansheng CHENG, Kuan ZHOU, Arnav GOEL, Subhra MAZUMDAR, Milad SHARIF, Po-Yu WU, Bowen YANG, Qi ZHENG
  • Publication number: 20230237013
    Abstract: A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.
    Type: Application
    Filed: September 9, 2022
    Publication date: July 27, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing LEUNG, Arnav Goel, Conrad Turlik, Milad Sharif
  • Publication number: 20230237012
    Abstract: A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors.
    Type: Application
    Filed: September 9, 2022
    Publication date: July 27, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing LEUNG, Arnav Goel, Conrad Turlik, Milad Sharif
  • Publication number: 20230229624
    Abstract: A computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system. Processors included in the compute nodes can execute compute workers of an application of the system and can form intranodal segments of an internodal interconnection topology communicatively coupling the intranodal segments. The intranodal segments can be interconnected via an internodal interconnections fabric. The TCC can determine the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric. The computing system can comprise the TCC and can comprise a data-parallel computing system.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 20, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg Dykema, Aarti Lalwani