Abstract: Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from a processor system (102) via a data bus (212, 214) and for modifying a state a clock-generation unit (106) having a local memory for controlling a plurality of clock outputs that provide clock signals for use by the processing system (102). The arrangement has a memory circuit (206) for storing the data from the processor system (102) and a control circuit (208) for accessing the data in the memory circuit (206) in response to a request to change a clock signal provided by an output of the plurality of clock outputs and for providing corresponding data to the local memory of the clock generation unit (106).

Abstract: A data processing system comprises a plurality of sub-circuits, a clock generator provided with a control circuit, a pool of oscillator circuits comprising at least three oscillator circuits, and a multiplexing circuit coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input coupled to a control output of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input of each of the sub-circuits. The control circuit is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.

Abstract: A data-processing system is described comprising: • A plurality of data-processing devices (11, 12, 13, 14) • A data-handling facility (20) shared by the data-processing devices, • An aggregation facility (30) for receiving signals (R1, R2, R3, R4) indicative for individual requirements from the data-processing devices for a performance of the shared data-handling facility and for providing a control signal (RA) indicative for a required activity level to meet the aggregated requirements, • a control device (40) for controlling an activity level of the data-handling facility depending on the control signal (RA). Additionally a data-processing method is described.

Abstract: Power-state transitioning arrangements are implemented using a variety of methods. Using one such method, a power-state transitioning circuit arrangement is implemented having a processing circuit that does not include an arithmetic logic unit. A power-state transition script including instructions from an instruction set is stored in a memory circuit. The processing circuit implements the power-state transition script to facilitate a change in a power-state of another processor circuit.

Abstract: A data processing system comprises a plurality of sub-circuits (10a, 10a, 10c), a clock generator (20) provided with a control circuit (22), a pool of oscillator circuits (24a, . . . 24f) comprising at least three oscillator circuits, and a multiplexing circuit (26) coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input (27) coupled to a control output (23) of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input (11a, 11b, 11c) of each of the sub-circuits. The control circuit (22) is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.

Abstract: Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from a processor system (102) via a data bus (212, 214) and for modifying a state a clock-generation unit (106) having a local memory for controlling a plurality of clock outputs that provide clock signals for use by the processing system (102). The arrangement has a memory circuit (206) for storing the data from the processor system (102) and a control circuit (208) for accessing the data in the memory circuit (206) in response to a request to change a clock signal provided by an output of the plurality of clock outputs and for providing corresponding data to the local memory of the clock generation unit (106).

Abstract: A data-processing system is described comprising: A plurality of data-processing devices (11, 12, 13, 14) A data-handling facility (20) shared by the data-processing devices, An aggregation facility (30) for receiving signals (R1, R2, R3, R4) indicative for individual requirements from the data-processing devices for a performance of the shared data-handling facility and for providing a control signal (RA) indicative for a required activity level to meet the aggregated requirements, a control device (40) for controlling an activity level of the data-handling facility depending on the control signal (RA). Additionally a data-processing method is described.

Abstract: Power-state transitioning arrangements are implemented using a variety of methods. Using one such method, a power-state transitioning circuit arrangement is implemented having a processing circuit that does not include an arithmetic logic unit. A power-state transition script including instructions from an instruction set is stored in a memory circuit. The processing circuit implements the power-state transition script to facilitate a change in a power-state of another processor circuit.