Patents by Inventor Greg F. Taylor
Greg F. Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7242261Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.Type: GrantFiled: October 6, 2003Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor
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Patent number: 7157924Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.Type: GrantFiled: October 10, 2003Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
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Patent number: 6985041Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.Type: GrantFiled: May 2, 2002Date of Patent: January 10, 2006Assignee: Intel CorporationInventors: Keng L. Wong, Niraj Bindal, Hong-Piao Ma, George Geannopoulos, Greg F. Taylor, Edward A. Burton
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Patent number: 6924710Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.Type: GrantFiled: September 9, 2003Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Robert Greiner, Edward A. Burton, Douglas R. Huard
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Patent number: 6809606Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.Type: GrantFiled: May 2, 2002Date of Patent: October 26, 2004Assignee: Intel CorporationInventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Robert Greiner, Edward A. Burton, Douglas R. Huard
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Patent number: 6778033Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.Type: GrantFiled: May 2, 2002Date of Patent: August 17, 2004Assignee: Intel CorporationInventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor
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Patent number: 6771134Abstract: A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.Type: GrantFiled: May 2, 2002Date of Patent: August 3, 2004Assignee: Intel CorporationInventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Edward A. Burton
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Patent number: 6747470Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.Type: GrantFiled: December 19, 2001Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
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Publication number: 20040085085Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.Type: ApplicationFiled: October 10, 2003Publication date: May 6, 2004Inventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
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Publication number: 20040080347Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.Type: ApplicationFiled: September 9, 2003Publication date: April 29, 2004Inventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Robert Greiner, Edward A. Burton, Douglas R. Huard
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Publication number: 20040070464Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.Type: ApplicationFiled: October 6, 2003Publication date: April 15, 2004Inventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor
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Publication number: 20030206067Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.Type: ApplicationFiled: May 2, 2002Publication date: November 6, 2003Inventors: Keng L. Wong, Niraj Bindal, Hong-Piao Ma, George Geannopoulos, Greg F. Taylor, Edward A. Burton
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Publication number: 20030206071Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.Type: ApplicationFiled: May 2, 2002Publication date: November 6, 2003Inventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Robert Greiner, Edward A. Burton, Douglas R. Huard
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Publication number: 20030206068Abstract: A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.Type: ApplicationFiled: May 2, 2002Publication date: November 6, 2003Inventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor, Chee How Lim, Edward A. Burton
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Publication number: 20030206072Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.Type: ApplicationFiled: May 2, 2002Publication date: November 6, 2003Inventors: Keng L. Wong, Hong-Piao Ma, Greg F. Taylor
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Publication number: 20030112027Abstract: An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die.Type: ApplicationFiled: December 19, 2001Publication date: June 19, 2003Inventors: Ali Muhtaroglu, Kent Callahan, Tawfik Arabi, Greg F. Taylor
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Patent number: 6298105Abstract: An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to “speed-up” the clock signals of the clock spines.Type: GrantFiled: October 30, 1998Date of Patent: October 2, 2001Assignee: Intel CorporationInventors: Xia Dai, George Geannopuolos, John Orton, Keng Wong, Greg F. Taylor
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Patent number: 6075832Abstract: An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.Type: GrantFiled: October 7, 1997Date of Patent: June 13, 2000Assignee: Intel CorporationInventors: George Geannopoulos, Keng L. Wong, Greg F. Taylor, Xia Dai