Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.

Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.

Abstract: A flip-flop circuit using AOI and OAI includes: a MUX unit with a multiplexer selecting between a first signal and a second signal; a master unit with two OAI, wherein the first OAI is coupled between a first node N1 and a third node N3, the second OAI is coupled between a second node N2 and a fourth node N4; a slave unit with two AOI, wherein the first AOI is coupled between the third node N3 and a fifth node N5, the second AOI is coupled between the fourth node N4 and a sixth node N6; and a clock for controlling the two AOI and the two OAI, the clock is connected to the first and the second AOI and the first and the second OAI.