Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

Abstract: The invention relates to a pendulous accelerometer including a pendulous electrode formed in a substrate, at least one counter electrode, and an encapsulation cover. The at least one counter electrode is formed under the cover, and spacers are positioned between the cover and the substrate.

Abstract: The invention relates to a pendulous accelerometer including a pendulous electrode formed in a substrate, at least one counter electrode, and an encapsulation cover. The at least one counter electrode is formed under the cover, and spacers are positioned between the cover and the substrate.

Abstract: A gate structure which includes a semiconductor substrate having a channel region, a gate insulator adjacent the channel region of the semiconductor substrate and a conductible gate adjacent the gate insulator. A primary insulation layer is adjacent the semiconductor substrate, the primary insulation layer having an opening where the gate insulator contacts the semiconductor substrate and an isolation dielectric layer adjacent the primary insulation layer, the isolation dielectric layer having an opening where the conductible gate is located and the isolation dielectric layer having a silicon oxynitride material.

Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

Abstract: A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation dielectric layer (26) may be formed adjacent the primary insulation layer (22). The disposable gate (24) may be removed to expose a portion of the primary insulation layer (22). The exposed portion of the primary insulation layer (22) may be removed to expose a portion of the substrate (12). The primary insulation layer (22) may be selectively removable relative to the isolation dielectric layer (26). A gate insulator (30) may be formed on the exposed portion of the substrate (12). A gate (32) may be formed adjacent the gate insulator (30).

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A structure and method for slowing down the etch rate of CVD oxide film 230 relative to the etch rate of thermal oxide 210 to prevent excessive removal of CVD oxide 230 during the stripping of the thermal oxide 210. Nitridation has been shown to be effective at retarding the etch rate of oxides. Therefore, nitridation of the CVD oxide 230 decreases the amount of oxide loss when thermal oxide 210 is etched. Nitridation of the wafer surface can be performed either before or after the nitride 200 removal step in standard process flows. In processes that use a densified CVD oxide 230, the densification of the CVD film 230 can be performed in an ambient that incorporates nitrogen in the film to significantly decrease the etch rate of the isolation oxide 230. Due to the porosity and the increased hydrogen content of the CVD oxide 230 as compared to the hydrogen content of thermal oxide 210, the nitrogen is incorporated more rapidly in the CVD oxide 230 than in the exposed thermal oxide 210.