Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.

Abstract: In one embodiment, an integrated circuit comprises at least one digital leakage detector that comprises digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a digital output representing the approximated magnitude. In another embodiment, a leak detector comprises leak circuits and clocked storage devices. Each leak circuit is configured to generate an output signal indicative of a different magnitude of leakage current in a transistor. The clocked storage devices are configured to capture a state representing the output signals of the leak circuits. In another embodiment, a method comprises running a test for leakage current in a digital leakage detector, wherein a digital output of the digital leakage detector represents a magnitude of a leakage current being experienced by the integrated circuit during use; and outputting the digital output from the integrated circuit.