Patents by Inventor Greg Horlick

Greg Horlick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8146042
    Abstract: An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: March 27, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Greg Horlick
  • Patent number: 7793249
    Abstract: Automatic bundle filtering is provided to selectively configure a circuit design having a plurality of component terminals for physical implementation. A placement of components is established for a layout of the circuit design, and a plurality of connections to be routed between predetermined terminals of the components are defined for the layout, with a certain plurality of them selectively grouped into at least one candidate bundle. At least one filter is applied to the connections of each candidate bundle for responsive segregation according to a preselected connection discriminant into one or more updated bundle candidates. Each updated bundle candidate is preferably evaluated in accordance with at least one preselected bundling criteria to identify acceptable bundle candidates therefrom. Bundles corresponding to the acceptable bundle candidates are then generated.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 7, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Greg Horlick, Randall Lawson
  • Patent number: 7620922
    Abstract: An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. The potential impact upon constraint compliance is evaluated, including generating a relative cost measure for the preliminary modification of the circuit routing solution, based at least partially upon each of the constraint instances.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Greg Horlick
  • Patent number: 7536665
    Abstract: A mechanism is provided for the user to define a circuit design intent or strategy in the form of data that is stored with the design database. An autorouter then uses this guidance from the user to create a plan for routing the design. The user can then modify their guidance to the router until the results for the plan are acceptable. Using the planned flow, the autorouter can complete the design, creating detailed paths including etch segments and vias. Allowing such interaction with an autorouter significantly reduces the routing time and hence time-to-market.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: May 19, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Greg Horlick, Randall Lawson, Donald Morgan, Paul Musto, Joe Smedley, Ken Wadland, Richard Woodward, Sean Bergan, Walter M. Katz