Abstract: Some of the embodiments of the present disclosure provide a method comprising providing an apparatus, wherein the apparatus is configured to be coupled to (i) a peripheral device and (ii) a host device. The apparatus includes memory configured to store logic, wherein the logic is configured to (i) allow the host device and the peripheral device to communicate with each other and (ii) operate the peripheral device. The apparatus further includes a processor configured to execute the logic. The method further comprises bundling the apparatus with a consumable product for sale with the consumable product, wherein the consumable product is configured to be consumed by the peripheral device.

Abstract: Some of the embodiments of the present disclosure provide a method comprising providing an apparatus, wherein the apparatus is configured to be coupled to (i) a peripheral device and (ii) a host device. The apparatus includes memory configured to store logic, wherein the logic is configured to (i) allow the host device and the peripheral device to communicate with each other and (ii) operate the peripheral device. The apparatus further includes a processor configured to execute the logic. The method further comprises bundling the apparatus with a consumable product for sale with the consumable product, wherein the consumable product is configured to be consumed by the peripheral device.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including an array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including a first array of interconnection sites, and a second array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the package substrate. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Abstract: A method and apparatus for protecting cache memories from soft errors. Entries in the cache's data store and tag memory are associated with parity bits. During a read cycle, the parity bits are checked and data retrieved only if the parity checks indicate no errors.

Abstract: A page printer includes a variable frequency clock for producing at least two clock frequencies, one higher than the other. The page printer includes a first memory for storing a page processing procedure and a second memory for storing data comprising full page strips. A processor operates at the first clock frequency in conjunction with the page processing procedure and derives a rasterization execution time (RET) for display commands that define images to be printed in each page strip of a page. The processor compares the RET for each page strip with a threshold value and rasterizes in the standard manner any page strip whose RET is equal to or less than the threshold value (while operating under the influence of the first clock frequency).

Abstract: A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates characteristics of the circuit module. The system also includes circuitry that enables the determination of the presence of other types of pluggable circuit modules in the connector. The circuitry comprises a latch circuit for holding a received address for the circuit module. In the received address, a preset field of bits is present which identifies a field in a status register. The status register stores n fields of information defining the characteristics of the pluggable circuit module and is responsive to the preset field of bits to provide signals on the predetermined pin set indicating the information.