Abstract: A method and system are directed to testing reconfigurable hardware designs, the method comprising inserting a scan chain into a reconfigurable hardware design associated with an integrated circuit comprising a redacted design; generating, using an automatic test pattern generation (ATPG) system, one or more test patterns and one or more bitstreams; receiving one or more primary outputs and contents of the scan chain from the reconfigurable hardware design by applying the one or more test patterns and the one or more bitstreams to the reconfigurable hardware design based on an ATPG test method of a plurality of ATPG test methods and a test architecture of a plurality of test architectures; comparing the one or more outputs and contents of the scan chain with one or more respective expected outcomes; and determining one or more faults associated with the reconfigurable hardware design based on the comparison.

Abstract: Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).

Abstract: Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).