Abstract: Techniques are provided to provide various pulse width modulation (PWM) schemes to embodiments of dual modulator display systems that may comprise a backlight of individually addressable and controllable light emitters. The backlight provides illumination to a light modulator for further conditioning of the light to be presented to a viewer. The backlight may be striped and each stripe is assigned a PWM scheme that effectively increases the bit depth of the controller for each stripe. The display system may allow a better matching of PWM periods to LCD frame rates to reduce visual artifacts. In another embodiment, the display system may detect a small bright feature to be rendered in the image data and, with a pre-assignment of light emitters to different partitions, the backlight controller may drive a subset of the light emitters according to the partitions.

Abstract: An apparatus is described having a plurality of network processors that identify, for each of a plurality of packets, which multidimensional queue from amongst a plurality of multidimensional queues that each one of the plurality of packets should be enqueued into. Each of the network processors is able to identify a particular multidimensional queue for a different one of the plurality of packets.

Abstract: An apparatus is described that includes a plurality of queuing paths. Each of the queuing paths further comprises an input queue, an intermediate queue and an output queue. The input queue has an output coupled to an input of the intermediate queue and the input of the output queue. The intermediate queue has an output coupled to the input of the output queue. The intermediate queue receives data units from the input queue if a state of the input queue has reached a threshold. The output queue receives data units from the intermediate queue if the intermediate queue has data units. The output queue receives data units from the input queue if the intermediate queue does not have data units.

Abstract: According to one embodiment, a network is disclosed. The network includes a source device, a networking hardware machine coupled to the source device, and a destination device coupled to the networking hardware machine. The networking hardware machine receives data packets from the source device and distributes statistics data corresponding to the data packets among multiple internal memory devices.

Abstract: A method is described that forms different pieces of a packet and sends each one of the pieces toward a different memory unit amongst a plurality of memory units. Each one of the memory units is managed by a different network processor. The method also receives each of the different pieces, each of the pieces having been read from its respective memory unit of the plurality of memory units.

Abstract: A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. An input buffer arrangement includes first and second buffer memories which each have a capacity to store one subframe. The first and second buffer memories are used alternatingly, with one storing a subframe of input data while another subframe is being read out of the other. A third buffer memory, which has a capacity to store at least one subframe, is provided upstream of the first and second buffer memories to prevent the first and second buffer memories from overflowing or underflowing.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.