Abstract: An apparatus provides an issue queue having a first section and a second section. Each entry in each section stores operation information identifying an operation to be performed. Allocation circuitry allocates each item of received operation information to an entry in the first section or the second section. Selection circuitry selects from the issue queue, during a given selection iteration, an operation from amongst the operations whose required source operands are available. Availability update circuitry updates source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. A deferral mechanism inhibits from selection, during a next selection iteration, any operation associated with an entry in the second section whose source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration.

Abstract: An apparatus and method are provided for operating an issue queue. The issue queue has a first section and a second section, where each of those sections comprises a number of entries, and where each entry is employed to store operation information identifying an operation to be performed by a processing unit. Allocation circuitry determines, for each item of received operation information, whether to allocate that operation information to an entry in the first section or to an entry in the second section. The operation information identifies not only the associated operation, but also each source operand required by the associated operation and availability of each source operand. Selection circuitry selects from the issue queue, during a given selection iteration, an operation to be issued to the processing unit, and selects that operation from amongst the operations whose required source operands are available.

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.

Abstract: The present invention relates to a method and system for controlling air traffic. The method and system utilizes aircraft performance data, provided either by an FMS of a capable aircraft or generated by a model based on knowledge of the aircraft, to provide an accurate prediction of aircraft intent so that an accurate estimated time of arrival can be generated. The estimated time of arrival is then used to provide a required time of arrival (RTA) for the aircraft. The RTAs for the aircraft are provided for the aircraft to arrive at a destination, such as an Outer Fix Point, in a desired sequence. The desired sequence is arranged to provide intervals between the aircraft such that they may be able to land at the destination airport without requiring holding and vectoring from top of descent.

Abstract: A methodology, system and business model are disclosed for facilitating a fully automated electronic identity service between a group of consumers and a group of service providers. The system includes at least one servicer and associated computers and memories. A security token is issued to the consumer by an authority. The consumer then personalizes the token by having his or her civil credentials loaded onto the card. The card is serialized by the authority. When the consumer desires access to a service, the system with authenticate the identity of the consumer. Various levels of authentication can be achieved. The service providers will subscribe to system.

Abstract: A system for detecting and registering serrated bags includes a web including a plurality of bags connected in an end-to-end arrangement, each bag including a first and second side, a first and second longitudinal end, a transverse seal, a serration disposed transversely across the bag, and a tab integrally connected to the bag at a portion of but less than the entire extent of the tab; a device for projecting a stream of air on each bag as the web passes a predetermined location; and a first and a second pair of nip rolls, each disposed downstream of the device, and adapted to accommodate the web, and to drive at different speeds such that a lead bag is separated from the web.

Abstract: The present invention relates to a method and system for controlling air traffic. The method and system utilises aircraft performance data, provided either by an FMS of a capable aircraft or generated by a model based on knowledge of the aircraft, to provide an accurate prediction of aircraft intent so that an accurate estimated time of arrival can be generated. The estimated time of arrival is then used to provide a required time of arrival (RTA) for the aircraft. The RTAs for the aircraft are provided for the aircraft to arrive at a destination, such as an Outer Fix Point, in a desired sequence. The desired sequence is arranged to provide intervals between the aircraft such that they may be able to land at the destination airport without requiring holding and vectoring from top of descent.

Abstract: The invention is a system and method for cardless secure on-line purchasing using a credit/debit card. There is provided an on-line purchaser executing an on-line purchase with an on-line vendor having a credit/debit card payment screen. There is also at least one on-line credit/debit card service provider having an interface with the on-line purchaser the said on-line vendor. An e-authentication and credential service provider has an interface with the on-line purchaser and said at least one on-line credit/debit card service provider and provides means for secure on-line purchasing on a subscription basis by providing anonymity to the on-line purchase by hiding credit/debit card data during the on-line purchase making the purchase invisible to identity thieves and hackers.

Abstract: A system for detecting and registering serrated bags includes a web including a plurality of bags connected in an end-to-end arrangement, each bag including a first and second side, a first and second longitudinal end, a transverse seal, a serration disposed transversely across the bag, and a tab integrally connected to the bag at a portion of but less than the entire extent of the tab; a device for projecting a stream of air on each bag as the web passes a predetermined location; and a first and a second pair of nip rolls, each disposed downstream of the device, and adapted to accommodate the web, and to drive at different speeds such that a lead bag is separated from the web.

Abstract: A personal video recorder records and plays back a television program in a user-defined playback mode while preserving content advisory rating information. A decoder parses a digital transport stream comprising transport stream packets containing the television program and generates navigation data. A source of content advisory rating information corresponding to said television program is provided. This source of content advisory rating information may be within the digital transport stream. A non-volatile storage unit is used for saving each of the frames of the television program in a transport stream file and for saving the navigation data in a navigation data file. The navigation data includes pointers that point to a location of each of the frames of the television program in the transport stream file and content advisory rating information associated with each of the frames from the source of content advisory rating information.

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

Abstract: A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.

Abstract: A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation—Internal Operations (NOP—IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

Abstract: A system and method for fetching noncontiguous blocks of instructions in a data processing system is disclosed. The system comprises an instruction cache means for providing a first plurality of instructions and branch logic means for receiving the first plurality of instructions and for providing branch history information about the first plurality of instructions. The system further includes an auxiliary cache means for receiving a second plurality of instructions based upon the branch history information. The auxiliary cache means overlays at least one of the second plurality of instructions if there is a branch in the first plurality of instructions and the branch is to the second plurality of instructions.

Abstract: An apparatus and method for renaming a plurality of storage register files implemented. A rename register in a unified rename buffer provides temporary storage for instruction operands resulting from the execution of the instruction to the operands being written to an architected register in one of storage register files. A rename map associates the rename register with the corresponding storage register, which may be in any of the storage register files. The rename registers may simultaneously store data values of different types. Rename map entries include a tag which operates to identify the register file containing the storage register.

Abstract: A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off.