Patents by Inventor Greg P. Chema

Greg P. Chema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of and apparatus for measuring the correctness of and correcting an automatic test arrangement
    Patent number: 6829553
    Abstract: A method of and an apparatus for determining the correctness of the calibration of an automatic test arrangement and correcting errors in the automatic test arrangement. The electrical length is determined from the tester driver of the automatic test arrangement to the socket pin of the tester interface unit, from the tester driver to a grounding point of the device under test, from the tester driver to the tester interface unit, and with the tester interface unit output pin connected to ground by a shorting block from the tester driver through the shorting block ground. The difference between the first electrical length and the second electrical length is compared with the difference between the first electrical length and the third electrical length, and the result is evaluated to determine the correctness of the calibration of the automatic test arrangement.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: December 7, 2004
    Assignee: Intel Corporation
    Inventors: Sunil K. Jain, Greg P. Chema
  • Method and apparatus for evaluating and correcting the tester derating factor (TDF) in a test environment
    Patent number: 6665627
    Abstract: Tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: December 16, 2003
    Assignee: Intel Corporation
    Inventors: Sunil K. Jain, Greg P. Chema
  • Method of and apparatus for measuring the correctness of and correcting an automatic test arrangement
    Publication number: 20020144197
    Abstract: A method of and an apparatus for determining the correctness of the calibration of an automatic test arrangement and correcting errors in the automatic test arrangement. The electrical length is determined from the tester driver of the automatic test arrangement to the socket pin of the tester interface unit, from the tester driver to a grounding point of the device under test, from the tester driver to the tester interface unit, and with the tester interface unit output pin connected to ground by a shorting block from the tester driver through the shorting block ground. The difference between the first electrical length and the second electrical length is compared with the difference between the first electrical length and the third electrical length, and the result is evaluated to determine the correctness of the calibration of the automatic test arrangement.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventors: Sunil K. Jain, Greg P. Chema
  • Method and apparatus for evaluating and correcting the tester derating factor (TDF) in a test environment
    Publication number: 20020143486
    Abstract: Tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventors: Sunil K. Jain, Greg P. Chema