Abstract: There is provided a parity check encoder (100) comprising a data memory (PPDM) configured for storing input data, a calculation/parity result data store (CPRDS), and a selector/serializer (SS). The CPRDS (104,106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SS (108) is coupled to the PPDM and CPRDS. The SS is configured to generate an encoded output sequence using the input data and parity bits. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix. A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: There is provided a parity check encoder (100) comprising a data memory (PROM) configured for storing input data, a calculation/parity result storage means (CPRSM), and a selector/serializer means (SSM). The CPRSM (104, 106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SSM (108) is coupled to the PPDM and CPRSM. The SSM is configured to generate an encoded output sequence using the input data and parity bile. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix, A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: A correlator includes a circuit for serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels and converting the data to blocks of n bit parallel I and n bit parallel Q signal data. At least one programmable read only memory (PROM) stores I and Q reference data. The memory receives and stores within each respective parallel I and Q signal channel a current block of n bit parallel I and n bit parallel Q signal data and the immediately previous received blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives the n bit parallel I and Q reference data and the n bit parallel I and Q signal data. The n bit parallel I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce a correlated I component signal output and a correlated Q component signal output.

Abstract: A correlator and method of correlating include a circuit that serially receives in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels at one input bit time periods and converts the data into blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives the signal and reference data. A multiplexer is positioned in each of the n parallel paths extending from the data bus and receives the n bit parallel I and Q reference data and a one bit shifted version of the respective n bit parallel I and Q signal data from the adjacent previous path. Each multiplexer includes I and Q summed outputs based on the value of I and Q reference data on a bit-by-bit basis. An n bit Wallace Tree Adder is connected to each of the I and Q summed outputs for each multiplexer within each of the n parallel paths and computes a count based on the number of bits that are set out of n bits to form partial correlation products.

Abstract: An automatic gain control (AGC) system includes at least one variable-gain component having a controllable gain over a gain control range and a sensor for sensing an amplitude of a signal from the at least one variable-gain control component. The sensor may have an operating window based upon the signal that is smaller than the gain control range of the at least one variable-gain component. The AGC system may also include a controller responsive to the sensor for controlling the at least one variable-gain component according to coarse and fine gain values to set the amplitude of the signal within the operating window of the sensor. The controller may implement at least one coarse gain jump from a current coarse gain value to a new coarse gain value when the sensor indicates the amplitude is outside the operating window. The controller may further implement movement to a fine gain value when the sensor indicates the amplitude is in the operating window.

Abstract: An automatic gain control (AGC) system includes at least one variable-gain component having a controllable gain over a gain control range and a sensor for sensing an amplitude of a signal from the at least one variable-gain control component. The sensor may have an operating window based upon the signal that is smaller than the gain control range of the at least one variable-gain component. The AGC system may also include a controller responsive to the sensor for controlling the at least one variable-gain component according to coarse and fine gain values to set the amplitude of the signal within the operating window of the sensor. The controller may implement at least one coarse gain jump from a current coarse gain value to a new coarse gain value when the sensor indicates the amplitude is outside the operating window. The controller may further implement movement to a fine gain value when the sensor indicates the amplitude is in the operating window.

Abstract: A correlator is disclosed and includes a data bus for receiving blocks of n bit parallel in phase (I) and n bit parallel quadrature (Q) signal data and n bit parallel I and Q reference data from respective I and Q signal channels and I and Q reference channels. The I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce an I component signal output and Q component signal output along each of the individual n parallel paths. An output bus receives I and Q component signal outputs from the n parallel paths one at a time at one bit input time periods such that there is one correlation product output for every I and Q parallel n bits. A cascade adder circuit comprises at least one adder connected to the output bus and receives the I and Q component signal outputs from the output bus and delayed I and Q component signal outputs from another correlator.