Abstract: A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as backed by an L2 cache.

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache.

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

Abstract: A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.

Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache.

Abstract: The presently disclosed subject matter is directed to a method of treating cancer, such as (but not limited to) metastatic bladder and breast cancer. The disclosed method comprises using two treatment modalities to synergistically treat primary and secondary tumor cells in a subject. The first element of the method comprises administering a therapeutically effective amount of a plasmonics-active metal nanoparticle to a subject comprising a primary cancer and a distant metastatic site, wherein the nanoparticle concentrates at the primary cancer. The method further comprises exposing the subject to photon radiation at the site of the primary cancer. The second element of the disclosed method comprises administering a therapeutically effective amount of an immune checkpoint modulator to the subject. The synergistic combination provides a rapid, safe, and effective treatment of local and distant lesions, better than each modality alone.

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

Abstract: The current disclosure relates to biomarkers for chemo-residual tumor cells cancer in a subject and methods of treating same.

Abstract: The presently disclosed subject matter is directed to a method of treating cancer, such as (but not limited to) metastatic bladder and breast cancer. The disclosed method comprises using two treatment modalities to synergistically treat primary and secondary tumor cells in a subject. The first element of the method comprises administering a therapeutically effective amount of a plasmonics-active metal nanoparticle to a subject comprising a primary cancer and a distant metastatic site, wherein the nanoparticle concentrates at the primary cancer. The method further comprises exposing the subject to photon radiation at the site of the primary cancer. The second element of the disclosed method comprises administering a therapeutically effective amount of an immune checkpoint modulator to the subject. The synergistic combination provides a rapid, safe, and effective treatment of local and distant lesions, better than each modality alone.

Abstract: The present invention discloses a system and method for generating and displaying review scores. The method includes obtaining product information of a consumer electronics product. The product information includes at least one metric. Further, the method includes utilizing the at least one metric to generate a consumer review score of the consumer electronics product.

Abstract: An anchoring system is provided for supporting a double-layered refractory lining of a process vessel. The refractory lining includes a first layer positioned adjacent to an inner surface of the process vessel and a second layer positioned adjacent to the first layer. The anchoring system has a plurality of bifurcated anchors extending from the internal surface of the process vessel through the first layer and into the second layer of the double-layered lining adjacent the first layer wherein the plurality of bifurcated anchors have a bifurcation disposed within the second layer.

Abstract: An anchoring system is provided for supporting a double-layered refractory lining of a process vessel. The refractory lining includes a first layer positioned adjacent to an inner surface of the process vessel and a second layer positioned adjacent to the first layer. The anchoring system has a plurality of bifurcated anchors extending from the internal surface of the process vessel through the first layer and into the second layer of the double-layered lining adjacent the first layer wherein the plurality of bifurcated anchors have a bifurcation disposed within the second layer.

Abstract: A process for the non-destructive testing of a refractory lined process vessel including the steps of: (a) striking an external wall of a process vessel internally lined with a refractory material with an impulse hammer; (b) measuring selected frequency characteristics of the refractory lined process vessel; and (c) analysing the measured frequency characteristics and determining the integrity of the internal lining of refractory material from the measured frequency characteristics.

Abstract: A process for the non-destructive testing of a refractory lined process vessel comprising the steps of: (a) striking an external wall of a process vessel internally lined with a refractory material with an impulse hammer; (b) measuring selected frequency characteristics of the refractory lined process vessel; and (c) analysing the measured frequency characteristics and determining the integrity of the internal lining of refractory material from said measured frequency characteristics.