Abstract: Embodiments of the present invention are directed to neuromorphic circuits containing two or more internal neuron computational units. Each internal neuron computational unit includes a synchronization-signal input for receiving a synchronizing signal, at least one input for receiving input signals, and at least one output for transmitting an output signal. A memristive synapse connects an output signal line carrying output signals from a first set of one or more internal neurons to an input signal line that carries signals to a second set of one or more internal neurons.

Abstract: A method for configuring nanoscale neural network circuits using molecular-junction-nanowire crossbars, and nanoscale neural networks produced by this method. Summing of weighted inputs within a neural-network node is implemented using variable-resistance resistors selectively configured at molecular-junction-nanowire-crossbar junctions. Thresholding functions for neural network nodes are implemented using pFET and nFET components selectively configured at molecular-junction-nanowire-crossbar junctions to provide an inverter. The output of one level of neural network nodes is directed, through selectively configured connections, to the resistor elements of a second level of neural network nodes via circuits created in the molecular-junction-nanowire crossbar. An arbitrary number of inputs, outputs, neural network node levels, nodes, weighting functions, and thresholding functions for any desired neural network are readily obtained by the methods of the present invention.

Abstract: In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.

Abstract: In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.

Abstract: Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a second embodiment of the present invention, two 3-state inverter circuits are combined to produce a transparent latch. The 3-state inverter circuit and transparent-latch circuit can then be used as a basis for constructing additional circuitry, including master/slave flip-flops, a transparent latch with asynchronous preset, a transparent latch with asynchronous clear, and a master/slave flip-flop with asynchronous preset.

Abstract: A method for configuring an associative array within a molecular-junction-nanowire crossbar, and nanoscale associative arrays configured by the method Keys are encoded as field-effect transistors selectively configured within the molecular-junction-nanowire crossbar, and values associated with keys are encoded as diodes selectively configured at molecular-junction-nanowire-crossbar junctions. Keys input into key registers result in a current signal indicating whether or not the key is stored within the associative array as part of a key/value pair and, if stored in the associative array, the value associated with the input key is output.

Abstract: A method for configuring any m-to-n multiplexer from a molecular-junction-nanowire crossbar, and m-to-n multiplexers configured according to the disclosed method. In the described embodiments, a complementary/symmetry molecular-junction-nanowire crossbar is employed, with input nanowire signal lines intersecting certain relatively high-voltage narrow nanowires via nFET devices and intersecting grounded nanowires via pFET devices. The relatively high-voltage and grounded nanowires are, in turn, selectively coupled to one or more output nanowire signal lines.

Abstract: Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a second embodiment of the present invention, two 3-state inverter circuits are combined to produce a transparent latch. The 3-state inverter circuit and transparent-latch circuit can then be used as a basis for constructing additional circuitry, including master/slave flip-flops, a transparent latch with asynchronous preset, a transparent latch with asynchronous clear, and a master/slave flip-flop with asynchronous preset.

Abstract: A method for configuring nanoscale neural network circuits using molecular-junction-nanowire crossbars, and nanoscale neural networks produced by this method. Summing of weighted inputs within a neural-network node is implemented using variable-resistance resistors selectively configured at molecular-junction-nanowire-crossbar junctions. Thresholding functions for neural network nodes are implemented using pFET and nFET components selectively configured at molecular-junction-nanowire-crossbar junctions to provide an inverter. The output of one level of neural network nodes is directed, through selectively configured connections, to the resistor elements of a second level of neural network nodes via circuits created in the molecular-junction-nanowire crossbar. An arbitrary number of inputs, outputs, neural network node levels, nodes, weighting functions, and thresholding functions for any desired neural network are readily obtained by the methods of the present invention.

Abstract: A method for configuring any m-to-n multiplexer from a molecular-junction-nanowire crossbar, and m-to-n multiplexers configured according to the disclosed method. In the described embodiments, a complementary/symmetry molecular-junction-nanowire crossbar is employed, with input nanowire signal lines intersecting certain relatively high-voltage nanowires via nFET devices and intersecting grounded nanowires via pFET devices. The relatively high-voltage and grounded nanowires are, in turn, selectively coupled to one or more output nanowire signal lines.

Abstract: An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.

Abstract: The present disclosure teaches a system for analyzing ultrasonic image that provides an output of a measurement of muscle width from an ultrasonic image input of an outline of a muscle from an animal or carcass. The muscle that is used in the preferred embodiment is the longissimus dorsi muscle when an ultrasonic scan is taken in a transverse direction relative to the backbone. The analysis is done with a computer that receives the electronic input of rows and columns of gray level pixel data from an ultrasonic scan image of the outline of the muscle of the animal or carcass. The software is set to select a region of the ultrasonic image input to analyze to determine a first edge of the muscle. The selected region is divided into subregions Sj,.sub.k. J designates a row and ranges between 1 and n. K designates a column and ranges between 1 and o such that o is greater than 1. The subregions are aligned in rows and columns throughout the ultrasonic image input.