Abstract: An apparatus and method estimates a plurality of synchronized phasors at predetermined times referenced to an absolute time standard in an electrical power system. The method includes acquiring and determining a frequency of a power system signal, sampling the power system signal at a sampling interval rate based on a frequency of the power system signal to form signal samples, and generating a plurality of acquisition time values based on an occurrence of each of the signal samples at a corresponding plurality of different times referenced to the absolute time standard. The method further includes adjusting a phasor of each of the signal samples based on a time difference between a corresponding selected acquisition time value and a predetermined time referenced to an absolute time standard to form the plurality of synchronized phasors.

Abstract: Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a phase difference between an absolute time reference signal and a compensated generated input signal, an IRIG encoder configured to couple a present time value with the generated output signal to form an IRIG waveform, a delay difference indicator configured to provide a time interval value based on a comparison of corresponding pulse edges of the generated output signal and the IRIG waveform, and a numerical delay component configured to delay the generated output signal by the time interval value to form the compensated generated input signal used to time-align the IRIG waveform with the absolute time reference signal to form the accurate IRIG waveform.

Abstract: The system for synchronous sampling uses an encoded time signal, such as an IRIG-B signal. The IRIG-B signal is applied to an edge detector, which produces pulses based on the edges of the encoded time signal. These signals are applied to a phase-locked-loop assembly which is arranged to produce an output sampling synchronization signal which is locked to the transitions in the encoded time signal, providing a synchronous control signal for data sampling of input signals to a plurality of electronic instruments, in addition to the use of the IRIG-B signal as time-of-day clock synchronization for the plurality of instruments.